Proceedings ArticleDOI
Shifting based VLSI scaler
TLDR
The main objective of the work is to develop a architecture which reduces the energy consumption of arithmetic modules and achieves more advantages than other architectures.Abstract:
Low power and reduced area with high performance digital adder are the main constraints in processors The main objective of the work is to develop a architecture which reduces the energy consumption of arithmetic modules Here both the multiplier and divider which perform up scaling and downscaling are embedded in a single shifting based architecture so that the area gets reduced and the power also reduces obviously Division is done by shifting and subtracting technique and multiplication also done by using the same shifter and adding technique to reduce the total area and power with better performance The speed of scaling is based on addition and subtraction operations speed in this architecture which are limited by carry and borrow propagations Carry select adder without multiplexer adder is used here in this architecture to overcome the speed limitation Carry select adder without multiplexer has less area and propagation delay which in term gives better performance addition and subtraction Validation of proposed design is done by designing and implementing it for a 16 bit scaler To prove its efficiency it is compared with existing division and multiplication architectures The performance analysis shows that the proposed architecture achieves more advantages than other architectures The techniques used here can be used or applicable to a variety of arithmetic modules which have similar characteristicsread more
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64-bit carry-select adder with reduced area
Young-Joon Kim,Lee-Sup Kim +1 more
TL;DR: A multiplexer-based add-one circuit is proposed to reduce the area with negligible speed penalty and requires 42% fewer transistors than the conventional carry-select adder.
Proceedings ArticleDOI
A low power and reduced area carry select adder
TL;DR: In the modified CSA, one of the n-bit adder blocks is replaced by an add-one circuit consisting of fewer transistors, which considerably reduces the power and area, with negligible speed penalty.
Proceedings ArticleDOI
Fast low-energy VLSI binary addition
TL;DR: Novel architectures for fast binary addition which can be implemented using multiplexers only are presented and it is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition.
Proceedings ArticleDOI
Performance comparison review of 32-bit multiplier designs
TL;DR: This study of a relative performance comparison of various 32-bits multiplier designs of Array, Wallace, Dadda, Reduced Area and Radix-4 Booth Encoding multipliers in the Area- Optimized, Speed-Optimized and Auto-optimized synthesis modes in Leonardo Spectrum concluded that Radix -4 BoothEncoding multiplier has the best findings in the area performance.
Proceedings ArticleDOI
Modelling and comparison of adder designs with Verilog HDL
D.J. Jackson,S.J. Hannah +1 more
TL;DR: The authors address various forms of adder design commonly encountered in microprocessor design and describe the process of modeling these designs at the gate level using the Verilog hardware description language (HDL).