Systolic array design space exploration of interpolators for multi-rate systems

TLDR: This study presents the development and comparison of interpolator systolic array designs and implementations and confirms that the proposed interpolator implementation requires no more than 61.7% of the hardware resources required in the conventional design and are at least 63.9% faster than theventional design.

Abstract: This study presents the development and comparison of interpolator systolic array designs and implementations. Systematic methodology was applied to the difference equations defining the interpolator algorithm. A dependence graph for the interpolator was obtained that combined the upsampler and the anti-imaging filter. Different data scheduling and projection operations were developed. Nine systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation. Field-programmable gate array implementations for the conventional and proposed designs confirm that the proposed interpolator implementation requires no more than 61.7% of the hardware resources required in the conventional design and are at least 63.9% faster than the conventional design.