Journal ArticleDOI
Technologies and building blocks for fast packet forwarding
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TLDR
The state of the art and the future of packet processing and switching are reviewed, and architectural and design issues that must be addressed to allow the evolution of packet switch fabrics to terabit-per-second throughput performance are discussed.Abstract:
We provide a review of the state of the art and the future of packet processing and switching. The industry's response to the need for wire-speed packet processing devices whose function can be rapidly adapted to continuously changing standards and customer requirements is the concept of special programmable network processors. We discuss the prerequisites of processing tens to hundreds of millions of packets per second and indicate ways to achieve scalability through parallel packet processing. Tomorrow's switch fabrics, which will provide node-internal connectivity between the input and output ports of a router or switch, will have to sustain terabit-per-second throughput. After reviewing fundamental switching concepts, we discuss architectural and design issues that must be addressed to allow the evolution of packet switch fabrics to terabit-per-second throughput performance.read more
Citations
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Patent
Multi-protocol and multi-format stateful processing
TL;DR: In this paper, a system and a method of processing data in a stateful protocol processing system (SPPS) configured to process a multiplicity of flows of messages is disclosed, which includes receiving a first plurality of messages belonging to a first of the flows comporting with a first-stateful protocol.
Patent
Switching arrangement and method with separated output buffers
TL;DR: In this paper, the authors propose a switching arrangement for transporting data packets from input ports of a switching device to output ports thereof, where the data packets comprise a payload and the switching device is able to route the arriving data packets according to data packet destination information to at least one dedicated of the output ports.
Patent
High speed network processor
Jean Calvignac,John Goetzinger William,Glen Howard Handlogten,Marco C. Heddes,Joseph Franklin Logan,James Francis Mikos,David Alan Norgaard,Fabrice Jean Verplanken +7 more
TL;DR: A Network Processor (NP) is formed from a plurality of operatively coupled chips as discussed by the authors, which includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow chip.
Proceedings ArticleDOI
NpBench: a benchmark suite for control plane and data plane applications for network processors
B.K. Lee,Lizy K. John +1 more
TL;DR: This work presents a set of benchmarks, called NpBench, targeted towards control plane as well as data plane workloads, and discusses the architectural characteristics of the benchmarks having control plane functions, their implications to designing network processors and the significance of instruction level parallelism (ILP) in network processors.
Journal ArticleDOI
IP router architectures: an overview
TL;DR: In this paper, the authors identify important trends in router design and outline some design issues facing the next generation of routers, and also observe that the achievement of high throughput IP routers is possible if the critical tasks are identified and special purpose modules are properly tailored to perform them.
References
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Journal ArticleDOI
Input Versus Output Queueing on a Space-Division Packet Switch
TL;DR: Two simple models of queueing on an N \times N space-division packet switch are examined, and it is possible to slightly increase utilization of the output trunks and drop interfering packets at the end of each time slot, rather than storing them in the input queues.
Journal ArticleDOI
The iSLIP scheduling algorithm for input-queued switches
TL;DR: This paper presents a scheduling algorithm called iSLIP, an iterative, round-robin algorithm that can achieve 100% throughput for uniform traffic, yet is simple to implement in hardware, and describes the implementation complexity of the algorithm.
Journal ArticleDOI
Design issues for high-performance active routers
Tilman Wolf,Jonathan S. Turner +1 more
TL;DR: The proposed design of a scalable, high-performance active router is used as a vehicle for studying the key issues that must be resolved to allow active networking to become a mainstream technology.
Journal ArticleDOI
On fast address-lookup algorithms
Hong-Yi Tzeng,Tony Przygienda +1 more
TL;DR: The theoretical limitations of routing table size are shown and one of the new algorithms proposed is almost optimal, while requiring only a small number of memory accesses to perform each address lookup, which is critical to the design of high-speed routing devices.
Journal ArticleDOI
A flexible shared-buffer switch for ATM at Gb/s rates
TL;DR: Owing to novel parallel structures inside the switch element, VLSI implementation is possible for transmission rates on the order of a gigabit per second per port and for a switch in a single-stage configuration as well as for the case of a three-stage switch fabric.