Journal ArticleDOI
Testing framework for on-board verification of HLS modules using grey-box technique and FPGA overlays
TLDR
RC-Unity, a heterogeneous unit testing framework that integrates FPGA-in-the-loop devices in order to extend the scope and capabilities of current HLS tools, is presented.About:
This article is published in Integration.The article was published on 2019-09-01. It has received 6 citations till now. The article focuses on the topics: Design flow & Unit testing.read more
Citations
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Journal ArticleDOI
FPGA-Based On-Board Hyperspectral Imaging Compression: Benchmarking Performance and Energy Efficiency against GPU Implementations
Julian Caba,María Auxiliadora Martín Díaz,Jesus Barba,Raul Guerra,José Alberto López,Sebastián +5 more
TL;DR: Results demonstrate that a solution based on the use of various instances of the FPGA hardware compressor core achieves similar levels of performance than the state-of-the-art GPU, with better efficiency in terms of processed frames by watt.
Proceedings ArticleDOI
Embedded Hardware Testing Using Bootloader
TL;DR: This paper presents how bootloader-based test software can benefit hardware production testing and suggests some key design requirements for developing a bootloader for testing hardware during production.
Proceedings ArticleDOI
A Comprehensive Investigation of Universal Verification Methodology (UVM) Standard for Design Verification
TL;DR: A Systematic Literature Review (SLR) is performed to identify 27 studies pertaining to UVM standard and concludes that UVM provides advanced phasing mechanism, reporting, callbacks, objections, sequence libraries and control over simulation as compared to OVM.
Journal ArticleDOI
FPGA-Based Solution for On-Board Verification of Hardware Modules Using HLS
TL;DR: This work introduces a framework for on-board verification of HLS-based modules by using reconfigurable systems and Docker containers with the aim to automate the verification process and preserve a clean testing environment, making the testbed reusable across different stages of the design flow.
Proceedings ArticleDOI
Bridging the Gap between Design and Verification of Embedded Systems in Model Based System Engineering: A Meta-model for Modeling Universal Verification Methodology (UVM) Test Benches
TL;DR: A novel meta-model for the modeling of Universal Verification Methodology (UVM) test benches is proposed in this article, based on the several UVM concepts like scoreboard, monitor, agent, driver etc in order to allow the simultaneous modeling of test benches along with system design.
References
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Proceedings ArticleDOI
Histograms of oriented gradients for human detection
Navneet Dalal,Bill Triggs +1 more
TL;DR: It is shown experimentally that grids of histograms of oriented gradient (HOG) descriptors significantly outperform existing feature sets for human detection, and the influence of each stage of the computation on performance is studied.
Journal ArticleDOI
High-Level Synthesis for FPGAs: From Prototyping to Deployment
TL;DR: AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx are used as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains.
Book
Probabilistic Graphical Models: Principles and Techniques - Adaptive Computation and Machine Learning
Daphne Koller,Nir Friedman +1 more
TL;DR: Because uncertainty is an inescapable aspect of most real-world applications, the book focuses on probabilistic models, which make the uncertainty explicit and provide models that are more faithful to reality.
Proceedings ArticleDOI
Dynamic Partial Reconfiguration in FPGAs
Wang Lie,Wu Feng-yan +1 more
TL;DR: A simple reconfigurable system that helps to reduce the configuration time and save memory as the partial reconfiguration files (bitstreams) are smaller than full ones.
Proceedings ArticleDOI
Beyond UVM for practical SoC verification
TL;DR: This paper shows standardized and well-organized testbench architecture that includes directory structure of testbench files, and mechanism such as interface and handles across the components, to build an efficient and structured verification environment which meets various requirements of SoC verification.