The Combined Input-Output Queued Crossbar Architecture for High-Radix On-Chip Switches

TLDR: This article proposes a novel microarchitecture that allows flat crossbar switches to scale to 128 ports, supporting 32 Gbits per second per port (Gbps/port) while occupying 4.9 mm^2 and consuming 4.2 W, and compares CIOQ with Swizzle Switch prototypes and demonstrates high-radix crossbars' potential for system-on-chip interconnects.

Abstract: High-radix, single-chip routers have emerged as efficient building blocks for interconnection networks. Researchers believe that hierarchical switch architectures are needed at high radices as crossbars scale with the square of the router radix. This article proposes a novel microarchitecture that allows flat crossbar switches to scale to 128 ports, supporting 32 Gbits per second per port (Gbps/port) while occupying 4.9 mm^2 and consuming 4.2 W, or supporting 64 Gbps/port at 7.5 mm^2 and 7.5 W, in 45-nm CMOS. Key features include deep crossbar pipelining to cope with wire delay, a novel cross-scheduler architecture to reduce wiring complexity, and catalytic custom gate placement within standard electronic design automation (EDA) flows. Furthermore, on a chip, crossbar speedup and combined I/O queuing (CIOQ) is better than hierarchical queueing, providing top performance with orders of magnitude lower memory cost. Finally, the authors compare CIOQ with Swizzle Switch prototypes and demonstrate high-radix crossbars' potential for system-on-chip interconnects.