Journal ArticleDOI
Threaded code
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The concept of “threaded code” is presented as an alternative to machine language code and hardware and software realizations of it are given.Abstract:
The concept of “threaded code” is presented as an alternative to machine language code. Hardware and software realizations of it are given. In software it is realized as interpretive code not needing an interpreter. Extensions and optimizations are mentioned.read more
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Journal ArticleDOI
Optimizing code‐copying JIT compilers for virtual stack machines
David Gregg,M. Anton Ertl +1 more
TL;DR: This paper uses a small domain specific language and tool to generate stack‐optimized code for sequences of virtual machine instructions, and for choosing the most useful sequences for a code‐copying compiler, and presents a novel system of optimizations based on exploiting common sequences ofvirtual machine instructions.
Proceedings ArticleDOI
An efficient interpreter for Datalog by de-specializing relations
TL;DR: The Souffle Tree Interpreter (STI) as discussed by the authors is a fast interpreter for Datalog that supports fast operations on relations in a virtual execution environment by de-specializing data structures.
Book ChapterDOI
Functional Specification of Process-Control Software
TL;DR: This paper focuses on functional program mming languages, which are based on the mathematical concept of recursive functions and define the desired result of a computation as a static input-output mapping.
Journal ArticleDOI
Edison-N—an Edison implementation for a network of microcomputers
TL;DR: An experimental implementation of the Edison programming language for a network of microcomputers based on the Z‐80 microprocessor allows parallel execution of concurrent processes to assist in teaching the principles of concurrent programming.
Simulation Native des Systèmes Multiprocesseurs sur Puce à l'aide de la Virtualisation Assistée par le Matériel : Native Simulation of Multiprocessor System-on-Chip using Hardware-Assisted Virtualization
TL;DR: In this paper, the authors propose a solution for the verification of the integration of multiple heterogeneous processors into a single System-on-Chip (SoC) by using a very long instruction word (Very Long Instruction Word) simulator.