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Proceedings ArticleDOI

Tunable stochastic computing using layered synthesis and temperature adaptive voltage scaling

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TLDR
This paper presents a framework wherein, the devices can operate at varying error tolerant modes while significantly reducing the power dissipated, and presents a novel layered synthesis optimization coupled with temperature aware supply and body bias voltage scaling to operate the design at various “tunable” error tolerance modes.
Abstract
With increasing computing power in mobile devices, conserving battery power (or extending battery life) has become crucial. This together with the fact that most applications running on these mobile devices are increasingly error tolerant, has created immense interest in stochastic (or inexact) computing. In this paper, we present a framework wherein, the devices can operate at varying error tolerant modes while significantly reducing the power dissipated. Further, in very deep sub-micron technologies, temperature has a crucial role in both performance and power. The proposed framework presents a novel layered synthesis optimization coupled with temperature aware supply and body bias voltage scaling to operate the design at various “tunable” error tolerant modes. We implement the proposed technique on a H.264 decoder block in industrial 28nm low leakage technology node, and demonstrate reductions in total power varying from 30% to 45%, while changing the operating mode from exact computing to inaccurate/error-tolerant computing.

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Citations
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Journal ArticleDOI

An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators

TL;DR: This article uses a two coupled nano-oscillator as a basic computational model and proposes an architecture for a non-Boolean coupled oscillator based co-processor capable of executing certain functions that are commonly used across a variety of approximate application domains, including an accuracy tunable knob.
Proceedings ArticleDOI

ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs

TL;DR: The paper proposes a Progressive Configuration Aware (ProCA) criticality analysis framework, that is 10X faster than the state-of-the-art, to identify logic which is functionally-critical to output quality, and demonstrates how a low powered tunable stochastic design can be derived.
References
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Proceedings ArticleDOI

Trading Accuracy for Power with an Underdesigned Multiplier Architecture

TL;DR: A novel multiplier architecture with tunable error characteristics, that leverages a modified inaccurate 2x2 building block, that can achieve 2X - 8X better Signal-Noise-Ratio (SNR) for the same power savings when compared to recent voltage over-scaling based power-error tradeoff methods is proposed.
Proceedings ArticleDOI

IMPACT: imprecise adders for low-power approximate computing

TL;DR: This paper proposes logic complexity reduction as an alternative approach to take advantage of the relaxation of numerical accuracy, and demonstrates this concept by proposing various imprecise or approximate Full Adder cells with reduced complexity at the transistor level, and utilizing them to design approximate multi-bit adders.
Proceedings ArticleDOI

Dynamic knobs for responsive power-aware computing

TL;DR: The experimental results show that PowerDial can enable benchmark applications to execute responsively in the face of power caps that would otherwise significantly impair responsiveness, and can significantly reduce the number of machines required to service intermittent load spikes, enabling reductions in power and capital costs.
Proceedings ArticleDOI

SALSA: systematic logic synthesis of approximate circuits

TL;DR: This work proposes SALSA, a Systematic methodology for Automatic Logic Synthesis of Approximate circuits, which encodes the quality constraints using logic functions called Q-functions, and captures the flexibility that they engender as Approximation Don't Cares, which are used for circuit simplification using traditional don't care based optimization techniques.
Journal ArticleDOI

Soft digital signal processing

TL;DR: A prediction-based error-control scheme is proposed to enhance the performance of the filtering algorithm in the presence of errors due to soft computations, and algorithmic noise-tolerance schemes can also be used to improve theperformance of DSP algorithms in presence of bit-error rates of up to 10/sup -3/ due to deep submicron (DSM) noise.
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