Book ChapterDOI
Understanding Clock Skew in Synchronous Systems
Mehdi Hatamian
- pp 87-96
TLDR
Three different clocking schemes, namely, edge-triggered, single-phase level sensitive, and two-phase clocking are considered and the effect of clock skew for any other clocking scheme can be analyzed and formulated.Abstract:
Clock distribution and synchronization in synchronous systems are important issues especially as the size of the system and/or the clock rate increase. Minimization of clock skew has always been a major concern for the designers. Many factors contribute to clock synchronization and skew in a synchronous system. Among the major factors are: the clock distribution network, choice of clocking scheme, the underlying technology, the size of the system and level of integration, the type of material used in distributing the clock, clock buffers, and the clock rate. To be able to get around the problems related to clock skew and synchronization, one has to understand the effect that clock skew can have on the operation of a given system. In this paper we derive simple and practical formulations of these effects in terms of a few time-parameters that can be considered as properties of the individual modules and the clock network in a synchronous system. Knowing these time-parameters, one can determine the maximum throughput of a given system as well as its reaction to a change in clock skew. Three different clocking schemes, namely, edge-triggered, single-phase level sensitive, and two-phase clocking are considered. However, using the approaches discussed in this paper, the effect of clock skew for any other clocking scheme can be analyzed and formulated.read more
Citations
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Journal ArticleDOI
Clock distribution networks in synchronous digital integrated circuits
TL;DR: A theoretical background of clock skew is provided and minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths.
Book
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TL;DR: This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design, and will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on- chip communication architectures.
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Synchronization in digital system design
TL;DR: The throughput of synchronous and asynchronous interconnect is compared and a discussion is presented of opportunities to apply principles long used in digital communications to the design of digital systems, with the goal of reducing the dependence on interconnect delay.
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Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits
TL;DR: A synchronous two-phase clocking scheme for RSFQ circuits of arbitrary complexity is introduced, which for critical circuit topologies offers advantages over previous synchronous and asynchronous schemes.
Journal ArticleDOI
An 85-MHz fourth-order programmable IIR digital filter chip
Mehdi Hatamian,Keshab K. Parhi +1 more
TL;DR: In this article, the authors describe the design and VLSI implementation of a single-chip 85-MHz fourth-order infinite impulse response (IIR) digital filter chip fabricated in 0.9-mu m CMOS technology.
References
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Journal ArticleDOI
Optimal interconnection circuits for VLSI
H.B. Bakoglu,James D. Meindl +1 more
TL;DR: In this article, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions, and propagation delays of aluminum, WSi 2, and polysilicon lines are compared.
Journal ArticleDOI
A 70-MHz 8-bit/spl times/8-bit parallel pipelined multiplier in 2.5-/spl mu/m CMOS
M. Hatamian,G.L. Cash +1 more
TL;DR: Clock skew, a major problem encountered in high-speed pipelined architectures, is overcome by the use of a balanced clock distribution network all on metal, and by proper use of clock buffers.
Journal ArticleDOI
Synchronizing Large VLSI Processor Arrays
TL;DR: This paper provides a spectrum of synchronization models; based on the assumptions made for each model, theoretical lower bounds on clock skew are derived, and appropriate or best possible synchronization schemes for large processor arrays are proposed.
Journal ArticleDOI
Parallel bit-level pipelined VLSI designs for high-speed signal processing
Mehdi Hatamian,G.L. Cash +1 more
TL;DR: Issues involved in designing fully pipelined VLSI architectures, including clock skew, clock distribution networks, buffering, timing simulation, area overhead due to pipelining, and testing are discussed.
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