Area of 128 bit shift register using cmos
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The area of a 128-bit shift register using CMOS technology varies depending on the design approach. Different studies have proposed efficient shift register designs with varying areas. For instance, a 128-bit shift register utilizing pulsed latches in a 65nm CMOS process occupied less area compared to traditional flip-flop-based designs . Similarly, a 128-bit unidirectional thermometer-code shift register in a 65nm CMOS process occupied 167μm², while a bidirectional version occupied 226μm², showcasing area reductions of 71% and 76% respectively compared to conventional designs . These examples highlight the potential for compact shift register implementations using innovative CMOS-based approaches.
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| Papers (4) | Insight |
|---|---|
06 Nov 1988 1 Citations | The paper discusses a 2 Gb/s GaAs 128-bit shift register using standard cells with 0.5 μm WN/sub x/ gate MESFETs, but it does not address the area of the shift register using CMOS technology. |
Open access•Journal Article | The 128-bit shift register using pulsed latches in a 65nm CMOS process with VDD = 1.0V saves area and power compared to a flip-flop-based register. |
01 Dec 2017 12 Citations | Not addressed in the paper. |
14 Mar 2011 10 Citations | Not addressed in the paper. |
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