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Open accessProceedings ArticleDOI
S. Augsburger, Borivoje Nikolic 
01 Sep 2002
40 Citations
Results show the advantages of multiple supply, transistor sizing, and multiple threshold can be compounded to maximize power reduction.
Transistor characteristics can be optimised in this way.
The technique can be coupled with transistor sizing to achieve the desired improvement in circuit delay.
In this paper, we propose a novel transistor-level optimization method.
In this paper, we propose a structure that improves the OFF state and switching behavior of the transistor without increase in the transistor length.
A new low voltage transistor could contribute greatly to the need for a new Vdd scaling scenario.
Here we demonstrate that such a heterojunction may be utilized to obtain a unique transistor operation.

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