Showing papers on "Adder published in 1972"

General purpose calculator with capability for performing interdisciplinary business calculations

Abstract: A battery-powered, hand-held, calculator employs MOS/LSI calculator circuits to perform arithmetic and financial calculations. Data and commands are input to the calculator from a keyboard having a prefix key to double the functions of selected keys. A 15-digit, seven-segment light emitter diode (LED) display serves as the output for the calculator. The calculator circuits include a read-only memory circuit in which the algorithms for performing the arithmetic and financial calculations are stored; a control and timing circuit for scanning the keyboard, retaining status information about the condition of the calculator or of an algorithm, and generating the next read-only memory address; and an arithmetic and register circuit containing an adder, a group of working registers, a group of data storage registers forming a stack for roll down operation, and a constant storage register. These circuits are interconnected by a multiple line buss system.

Pipelining of Arithmetic Functions

Abstract: Two addition and three multiplication algorithms were studied to see the effect of pipelining on system efficiency. A definition of efficiency was derived to compare the relative merits of various algorithms and implementations for addition and multiplication. This definition is basically defined as bandwidth cost. Previous comparisons of adders and multipliers have generally been based on latency. In a pipeline environment, latency (or its inverse bandwidth) is not as important. Any bandwidth is possible up to the physical limitations on gate delay variations and pulse skew. The formal definition for efficiency is efficiency = N/D·G where N is the number of bits in the operands, D is the delay (uniform) of each pipeline stage in units of gate delays, and G is the total number of gates, including any used for latching. In cases where gate variations and pulse skewing are well defined, pipelining using the Earle latch results in increased efficiency. The most efficient adder is a maximally pipelined conditional-sum adder (three stages with a delay of four gates per stage). Its efficiency is 6.30×10-3. The most efficient multiplier is a maximally pipelined tree multiplier (eight stages with a delay of four gates per stage). Its efficiency is 3.48×10-4.

Analysis and simulation of networks of mutually inhibiting neurons.

Abstract: Networks of mutually inhibiting neurons are analyzed and simulated on a digital computer. In the analysis and simulation a continuous-variable model of the neuron is used as the basic element. It consists of a many-input adder, a first-order low-pass filter and a diode-type nonlinearity. A mutually inhibiting network is formed by connecting the output of every element to inputs of the other elements through weight-coefficient setting units. Each element of the network is assumed to receive a certain number of constant inputs from elements of other networks.

Electric circuit for the production of a number of different codes

Abstract: An electric circuit, in particular for devices and systems operating on an SSMA basis, for the production of a number of different codes according to a linear law of formation and having practically negligible values of cross correlation coefficients and autocorrelation coefficients during a shifting time and characterized by the provision of two basic code generators respectively consisting of a sequential network, at least one-half adder and at least one delay network, the half adder representing the output circuit, wherein one of the two codes is respectively given at both outputs of the half adder and the delay network is arranged in the connection path which extends between one of the two basic code generators and the half adder.

Limit cycles due to adder overflow in digital filters

Abstract: In this paper we study the control of the amplitude of () EA limit cycles due to adder overflow which occur in the zero-input response of second-order digital filters. We consider a digital filter model in which the effects of quantization (i.e., roundoff, truncation, etc.) are included. Our analysis is sufficiently general in character that consideration is given to a wide variety of types of arithmetic. In addition to our new results, virtually all of the previously known results concerning such limit cycles also follow from our analysis. Since our results are all obtained by a single technique, the work thus tends to unify the body of knowledge in this area. Furthermore, our technique is easily generalized, and there is reason to believe that such generalizations could also be profitably applied to the analysis of higher order systems.

Video image positioning control system for amusement device

Abstract: For controlling the location of an image and to cause the image to move variously with respect to perpendicular coordinates, such as X, Y coordinates, on a video display tube, a first set of counters is arranged to generate artificial, horizontal and vertical sync pulses for use in conjunction with a video adder for controlling the image on a TV screen. A second set of counters driven from the same clock source as the first supplies information signals to the video adder for controlling the location at which the image will be displayed. Each of the two predetermined counters constituting the second set of counters is capable of being preset to any of a plurality of counts so as to cause a horizontal or vertical displacement of the image on the face of the display tube with respect to the locus defined by the count generated by the first set of counters.

Pseudo-random number generators

Abstract: A pseudo-random number generator produces a substantially Gaussian distribution of output numbers from a succession of uniform random numbers. In each cycle uniform random numbers are produced and applied to an adder operative to form cumulative sums. A counter is responsive to carry signals from the adder and the outputs of the adder and counter are combined to form an output pseudo-random number. The number of permitted adding operations is preset.

Multifunction full adder

Abstract: An arithmetic unit which may be utilized in any binary computational circuit. The arithmetic unit utilizes a pair of exclusive OR gates connected in series. One of the exclusive OR gates operates upon input signals (e.g. addend and augend) to produce an output signal. The other exclusive OR gate operates upon input signals (e.g. carry and output from the first OR gate) to produce the sum output signal. A two-way transmission gate switch operates upon certain input signals (e.g. carry, addend or augend, and output signal produced by the first exclusive OR gate) to produce the carry output signal.

Some effects of quantization and adder overflow on the forced response of digital filters

Abstract: The effects of quantization (i.e., roundoff, truncation, etc.) and adder overflow, which are present in any special-purpose computer type realization of a digital filter, cause an otherwise linear system to become quite nonlinear. Moreover, the presence of such nonlinearities can cause the system's response to differ drastically from the ideal response (that is, from the response of the linear model of the filter) even when the level of the filter's input signal is, in a certain reasonable sense, small, and when the quantization effects are made arbitrarily small. In this paper we derive a criterion for the satisfactory behavior of second-order digital filters in the presence of such nonlinear effects. The criterion is shown to be sharp, in that we also present a procedure for constructing counterexamples which show that, for most filters which violate the criterion, the response to some “small” nonzero input signal is not always even asymptotically close to the ideal response.

Digital diversity combiner

Abstract: This relates to a predetection maximal ratio digital diversity combiner for a phase shift keyed digital data signal propagating on N different paths through a dispersive medium, where N is an integer greater than one. Each of N signal channels respond to the data signal propagated on a different one of the N different paths. Each of the channels include an arrangement to separate the data signal into an inphase component and a quadrature component and also a pair of analog-to-digital converters to convert the inphase component into an inphase digital signal and the quadrature component into a quadrature digital signal. A digital adder arrangement is coupled in common to the output of each of the N channels to digitally add the inphase digital signal of each of the channels together to produce a combined inphase digital signal and to digitally add the quadrature digital signals of each of the channels together to produce a combined quadrature digital signal. A decision circuit responds to the most significant digit of both the combined inphase digital signal and the combined quadrature digital signal to recover the data conveyed by the data signal. A clock recovery circuit responds to the combined inphase digital signal, the combined quadrature digital signal and the recovered data to produce properly phased timing signals for control of the decision logic, each of the analog-to-digital converters and an automatic gain control circuit common to each of the N channels. Each of the channels further include an arrangement coupled between the associated pair of analog-to-digital converters and the digital adder arrangement and also to the decision circuit. This arrangement is responsive to the recovered data and the inphase and quadrature digital signals to determine the maximal ratio weights of these signals. The determined inphase and quadrature digital weight signals are employed to weight the inphase digital signal and the quadrature digital signal prior to digitally adding thereof in the adder arrangement. An automatic gain control circuit is coupled to the last mentioned arrangement of each of the channels and to the clock recovery circuit to produce an automatic gain control signal to control the gain of the data signal in each of the channels. This is accomplished by detecting the maximum maximal ratio weight of either the inphase or quadrature digital signal of any of the channels involved in the diversity combiner and generating from this maximum maximal ratio weight an automatic gain control voltage.

Carry skip-ahead network

Abstract: A network for use with arithmetic units such as adder circuits wherein a large number of bits are added together. Provision is made for evaluating the added bits in conjunction with the carryin signal supplied to the adder so that the carry signal may be ''''skipped ahead,'''' i.e. passed over, one or more adder circuit segments in order to avoid the delay of propagating a carry signal through each adder circuit segment in the arithmetic unit.

Dual output adder and method of addition for concurrently forming the differences a{31 b and b{31 a

Abstract: Disclosed is an adder and a method of addition for use in a data processing system The adder concurrently produces from operands A and B dual outputs which are the difference A-B and the difference B-A The dual outputs from the adder are used in exponent arithmetic where the smaller operand is subtracted from the larger operand At the time the subtraction commences it is not known which operand, A or B, is larger and therefore whether A-B or B-A is desired The dual output adder insures that the desired subtraction, either A-B or B-A, is available at a time which does not delay processing of the exponent arithmetic instruction

Binary carry lookahead adder using redundancy terms

Abstract: Disclosed is an adder for use in a data processing system. The adder includes five levels of logic circuits for forming bit propagate, bit generate, group propagate, half-sum internal carry and full-sum terms. Additionally, redundancy Z terms are introduced which, together with bunch propagates and bunch generates produce external carries which are combined to generate the full-sum terms. The inclusion of redundancy in terms enables a factoring of terms which reduces the fan-in and fan-out requirements within the adder.

Two-bit binary divider

Abstract: Method and apparatus for performing 2-bit, non-restore, lookahead, binary division for a digital processor wherein 2 quotient bits are generated simultaneously during one adder cycle; the cycle length needed to develop these 2 bits being essentially limited to the time needed by the adder to perform subtraction. A multiple of the divisor to be subtracted from four times the remainder (4R - MD) for the succeeding cycle is selected concurrently with the remainder developed as a result of the subtraction. A table and decoder are preferably used to examine the magnitudes of the remainder and the divisor to predict this multiplication factor which may also be developed tentatively into the 2-bit quotient. A correction may then be made to the tentative quotient as a result of the adder operation, the corrected quotient being entered into the quotient register.

Partial product array multiplier

Abstract: A multiplier comprising a partial product array means for receiving an m-bit multiplier and an n-bit multiplicand for generating a partial product array of numbers in a plurality of columns. Each of the columns is connected to a multi-operand adder capable of simultaneously adding m-bits.

Electronic digital clock apparatus

Abstract: A plurality of shift registers for storing time information represented by numbers consisting of a plurality of digits are connected to an adder to form a closed loop. The time information stored in the shift registers is circulated through the closed loop in a minimum unit length of time. When the adder is supplied with information on the minimum unit length of time, it receives a single addition pulse per minimum unit length of time. A decoder is supplied with four bit outputs from a shift register corresponding to a particular digit position, and outputs from the decoder are supplied to a plurality of digit indicators in common. The digit indicators are successively impressed with operating voltage to display time information periodically.

Threshold logic overflow detector for a three-input adder

Abstract: A threshold logic overflow detector for a three-input adder is a combination of storage-processor elements and a pair of busses arranged so that three input-word sign-bits, a sum-word sign-bit, and at least one carry-bit from the adder are stored in separate storage-processor elements for controlling units of current conducted through the busses. Predetermined potentials are established on the busses in response to the units of current conducted therethrough. Two additional storage-processor elements respectively compare the potentials on the busses with a predetermined reference potential and thereby determine the occurrence and polarity of any net overflows that occur in the three-input adder.

On Error Control in Sequential Machines

Abstract: It is shown that if a machine M con be mapped into a simpler machine M' by a homomorphism, then an error correcting/detecting code can be applied to the states of M such that the parity check bits are generated independently of the information bits that form the state assignment of M. If such a homomorphism does not exist, it is shown how to produce one by altering M if M consists entirely of loops as is the case with a digital computer. The method presented here is a generalization to sequential machines of the separate adder and checker concept used for checking addition. Methods of coding are given. Application to computers is given.

Digital high order interpolator

Abstract: A system is disclosed herein which is designed to generate the value for dependent variables of given mathematical functions when provided with corresponding independent variables as inputs thereto by computing a Taylor Series Expansion of that function. Any function for which a Taylor Series Expansion exists in the region of interest may be generated by the disclosed system. A read-only memory is disposed for storing a plurality of predetermined parameters of a Taylor Series Expansion for each function to be computed. An asynchronous binary product generator and a binary adder are provided, external to the read-only memory, for performing cyclic computations of the Taylor Series Expansion. A control circuit is provided for synchronizing the operation of the individual constituent circuits.

Carry generation means for multiple character adder

Abstract: An addition stage of a binary multiple character adder is receptive to input signals, including operand bits from each of the characters and carry-in bits from previous lower order stages. The outputs include the sum for that stage and carry-out signals to succeeding higher order stages. Means are provided for determining the pattern of the input signals and for generating at least one carry-out signal from another carry-out signal in accordance with the input pattern.

Error detection for arithmetic and logical unit modules

Abstract: A modular error detector for an adder of the type which provides both arithmetic and logical functions and incorporates carrylook-ahead addition is described The error detector includes parity prediction of logical and arithmetic terms together with partial duplication Error checking of four bit arithmetic/logic modules is integrated with error checking of the carry-look-ahead unit Also, check parity generation and testing of the operands is integrated with the parity prediction

Distance or speed measuring apparatus for land-vehicles

Abstract: A representation of the distance travelled by, or the speed of, a wheeled-vehicle and compensated for wheel-slip, is provided from signals derived in accordance with the speeds respectively of two driven wheels of the vehicle Difference between the two signals arising from slip is detected to derive a difference signal that is subtracted from the sum of the two signals so as to derive thereby an output in accordance with the speed of the slower, non-slipping, wheel Alternatively, the difference signal controls switches that supply the two signals to an adder to cause both to supply the slower-wheel signal to the adder when a predetermined threshold value of the speed-difference signal is detected The sense of the speed-difference signal may instead be used to control selection for direct use of whichever of the two wheel-speed signals is representative of the slower wheel The two speed signals may be in the form of mechanical or electrical manifestations and in the latter case may be of pulse form supplied to respective switching inputs of a bistable device to produce an output pulse train in accordance with the lower pulse frequency Where two wheels are driven from a common drive-shaft through a differential, detected rotation of the planet wheels of the differential (arising from slip of one driven wheel relative to the other) may be used to reduce the engine speed so as to eliminate slip and ensure correct reading of speed or distance directly from the drive-shaft rotation

Digital bit synchronizer

Abstract: A system for deriving synchronizing pulses from a train of digital signals that is fed to in-phase and mid-phase gates each including an adder with a delay feedback. The output of the midphase gate is multiplied by a sign factor determined by a logic circuit connected to the in-phase gate. The output of the two gates are then mixed, filtered, and summed with a value dependent upon the clock rate and fed to a number controlled oscillator which includes a counter and a comparing circuit. The output of the number controlled oscillator is fed back to the in-phase and mid-phase gates.

Circuits and methods for processing delta-modulated signals

Abstract: A delta-modulated signal processing circuit includes one or more first multipliers for multiplying one or more delta-modulated input signals by preselected constants, thus producing a first code signal corresponding to each first multiplier. A second multiplier is provided for multiplying a delta-modulated output signal by a second constant having a sign opposite to that of the first constants to provide a second code signal. A digital adder takes the algebraic sum of the first and second code signals. The output of the digital adder is applied to an integrator to produce an output signal including sign-indicating bits. Also included in the circuit is a sign-bit extractor for extracting the sign-indicating bits from the output of the integrator. This provides the delta-modulated signal supplied to the second multiplier. Modifications of this circuit for various uses are disclosed.

Binary adder using josephson devices

Abstract: A binary adder using Josephson devices for the sum and carry gates is disclosed. A gating current Ig1 is applied to a Josephson device operating as a sum gate, and a gating current Ig2 is applied to a Josephson device operating as a carry gate. Each of said Josephson devices switches from v = 0 to v NOTEQUAL 0 when the control current applied thereto lowers the critical gating current below the applied gating currents Ig1 and Ig2 respectively. The binary bits to be added, A, B, and Carry, C, from the prior stage, are applied to the Josephson devices as control currents Ix. The sum gate switches to v NOTEQUAL O, corresponding to a sum bit output, S, when the total control current is Ix or 3I x. The carry gate switches to v NOTEQUAL o, corresponding to a carry bit output, C, when the total control current is 2I x or 3I x.

Discovery in a fluidic computer

Abstract: A device for calculating and displaying the total gasoline sale price at a gasoline pumping station. A unit price selecting and displaying mechanism controls three fluidic encoders which translate the unit price of gasoline into binary-coded decimal numbers representing tenths, hundredths, and thousandths of a cent respectively. Fluidic decade circuits representing tenths, hundreds and thousandths of a cent respectively are arranged to receive these outputs from the encoders, so that the appropriate cost amounts are added in each decimal digit position. The addition is performed in response to each one of a series of fluidic ''''add'''' pulses from a gasoline flowmeter. Each decade circuit includes a BCD adder receiving an addend input from its associated encoder, a BCD accumulator which receives the adder sum output, and a return path which reinserts the accumulator total as an augend input into the BCD adder. In response to the flowmeter pulses, the adder adds the unit price digit available from the encoder to the previous total available from the accumulator, and thus generates a new total for the accumulator. Each decade circuit develops a carry output to the next more significant decade.

Tunnel diode full binary adder circuit

Abstract: A simple full binary adder circuit employing a tunnel diode and a transistor is proposed. It has a well defined operation and is capable of operating at rates up to 200 MHz.

Apparatus for providing an analog or the like of the angular velocity of a rotating body

Abstract: Two magnetic pickups are fixed around a toothed, ferromagnetic rotating wheel in positions such that they produce output signals which are approximately sine wave in shape and in phase quadrature. Each pickup output is introduced to a different corresponding multiplicative mixer. One mixer receives a carrier input in addition. The other mixer receives the carrier shifted in phase by 90*. The outputs of mixers are introduced to an adder. The output of the adder is then free of carrier upper sideband. The lower sideband may then, if desired, be transmitted over long distances without a loss of accuracy. A.D.C. voltage, if desired, may then be developed directly proportional to the frequency of the lower sideband by a frequency discriminator. This voltage is then directly proportional to the wheel velocity. Moreover, the resolution of this volocity analog is high and to within one cycle of the high carrier frequency.

Multiple operand addition and multiplication

Abstract: Traditionally, adders used in small- and medium-sized computers are designed to add two n-bit numbers. There are arithmetic operations which require the addition of a large number of numbers. Multiplication (division) and special function generation are such operations. In large computers, "carry save addition", which adds a group of 3 numbers and reduces their sum to a partial sum of two numbers, has been frequently used to speed up multiplication. One of these two partial sums evaluates the sum modulo 2 of bits in the same binary order; the second partial sum being composed from carries generated but not transferred. These partial sums are regrouped in triplets and enter a "carry look ahead" adder to provide the final sum. The circuit implementation is a cascade connection of full adders, and is referred to in the literature as "adder tree". The operation time is considerably reduced because carries are not transferred, although they are formed.

Storage-processor element including a bistable circuit and a steering circuit

Abstract: Disclosed is a storage-processor element, designed so that groups of such elements can be interconnected into threshold logic circuits. Each element is arranged to decide which one of a pair of double-rail input signals has a higher potential and to store the result of that decision. Information read out of storage directs a unit of current to one or the other of two output busses. A threshold logic adder circuit and a threshold logic two''scomplement circuit use combinations of the storage-processor elements.