Showing papers on "Analog-to-digital converter published in 1991"

Sigma-delta oversampled analog-to-digital converter network with chopper stabilization

Abstract: In an oversampling interpolative analog-to-digital converter having a sigma-delta modulator followed in cascade by a decimation filter, the decimation filter supplies digital output signals for the oversampling analog-to-digital converter at an output rate that is a submultiple 1/R of an oversampling rate at which digital samples of an input signal for said decimation filter are supplied. The chopping rate of the chopper-stabilized amplifier is a multiple of the output sample rate of the decimation filter to place the fundamental and the harmonics of the chopping at the frequencies corresponding to the zeroes in the decimation filter response, better to keep remnants of the chopper stabilization from appearing in the output samples from the decimation filter. The chopper stabilization moves the flicker (or 1/f) noise of the amplifier in the frequency spectrum from baseband to sidebands of the chopping frequency, and the chopper-stabilized amplifier is operated at a chopping rate higher than said output rate, to reduce the amplitude of the lower sideband as aliased into the baseband. The chopper-stabilized amplifier is operated at a chopping rate lower than half said oversampling rate, to reduce non-linearities associated with the settling of the chopper stabilized amplifier after each switching thereof.

Multi-stage sigma-delta analog-to-digital converter

Abstract: A precision sigma-delta A/D converter having a desired number of cascaded stages is disclosed herein. The multi-stage sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal X(z) to an output sequence of digital words. The converter (10) of the present invention includes a first sigma-delta converter stage (14) for generating a first sequence of digital words and a quantization error signal in response to the analog input signal X(z). An interstage amplifier (34) then amplifies the quantization error signal by a first gain factor G. The present invention further includes a second sigma-delta converter stage (18) for generating a second sequence of digital words in response to the amplified quantization error signal. The first and second sequences are next filtered by a digital noise cancellation network (31, 32) and the filtered second sequence is divided by the first gain factor G via a divider circuit (38). A summing circuit (40) provides the output sequence of digital words by summing the filtered first sequence and the divided second sequence. The digital noise cancellation network (32) is also used to compensate for errors due to analog component imperfections, e.g., capacitor mismatches and finite operational amplifier gain.

Synchronous digital detection of position error signal

Abstract: A sample data position error signal detection means. This invention has application in a digital servo in a magnetic media disk drive environment. In particular, the invention relates to the detection in digital form of position error signals (PES) representative of magnitude and sign of recording head displacement from a track center line. The circuits disclosed provide a digital representation of PES suitable for direct application to a digital signal processor which controls overall servo positioning operations. The invention detects the PES by employing a digital integrator which comprises a register and adder. The composite servo data is first amplified by variable gain amplifier and then undergoes low pass filtering before being digitized by an analog to digital converter (ADC). The digital integration is performed by accumulating a constant number of ADC samples in the register. Before being accumulated in the register, the sampled servo data is alternately multiplied by plus or minus one, using an exclusive-OR gate cascade interposed between the ADC output and adder input. The multiplication of the sampled servo data by plus one or minus one is required for synchronous rectification. Upon completion of accumulation of a prescribed number of ADC samples, the contents of the register are transferred to a temporary buffer pending interrogation by the servo controlled digital signal processor.

The oversampling technique for analog to digital conversion: a tutorial overview

Abstract: Oversampled technique has received wide attention in the VLSI implementation of analog to digital interface. The technique relies on the fundamental principle of trading off temporal resolution with amplitude resolution. This trade-off allows the ADC (Analog to Digital Converter) to achieve resolution beyond the limitations imposed by the matching tolerance of fine line VLSI technology. In addition it simplifies the overall system design by relaxing the front end anti-aliasing requirement.

Two-step subranging analog to digital converter

Abstract: A subranging analog-to-digital converter (ADC) that comprises a biasing architecture including a single string of transistor current sources used to generate the reference digital-to-analog converter (DAC) bit currents, the low-resolution flash ADC reference ladder voltage, and the ADC bipolar offset voltage. The reference DAC resistors, low resolution voltage reference ladder resistors, error amplifier gain set resistors, and the bipolar offset resistors are all constructed from the same material and using the same physical construction, so that they match with high precision and track over process and temperature. In one embodiment, the low-resolution flash ADC is itself implemented as a two-step parallel subranging ADC, comprising a most-significant-bit reference ladder and a least-significant-bit reference ladder, and includes an internal flash DAC whose bit currents are also provided by the same single string of transistor current sources. In addition, a shunt resistor across the least-significant-bit reference ladder of the low-resolution flash ADC makes it possible to tie it in series directly to its most-significant-bit reference ladder using the same resistor material, thus providing inherent tracking of the reference voltages of the two ladders. Finally, a bias current compensation resistor network is provided on the input side of the flash ADC comparators to cancel input bias current errors.

Digital electronic still camera having removable record means

Abstract: A digital electronic still camera wherein additional information such as an operation characteristic of the camera can be recorded into and reproduced from a removable record medium. A pickup image signal is picked up by a CCD image sensor and converted into a digital signal by an analog to digital converter. The digital signal is temporarily stored into a digital memory and written onto a removable optical disk apparatus. The digital electronic still camera further comprises an additional information recording and reproducing circuit for recording and reproducing additional information such as an operation characteristic of the camera onto or from the optical disk apparatus.

Continuously integrating high-resolution analog-to-digital converter

Abstract: A continuously integrating analog-to-digital converter (ADC) calculates a digital output by integrating an input voltage over a number of time intervals using a multisloping technique to define the input voltage in terms of a slope count. A residue ADC is used in lieu of a run-down interval of the integrator to calculate the least significant bits of the ADC digital output. This is accomplished by first sampling the integrator output voltage, and then after a number of time intervals, sampling the integrator output voltage a second tune. The difference between the two residue voltages is converted into a fractional slope count by multiplication with a calibration constant. The fractional slope count can then be added to the slope count from the integrator, so that the resulting total slope count is directly proportional to the input voltage at a high resolution. Multiplication by the calibration constant may be effectuated by controlling the gain on the residue ADC with a digital-to-analog converter (DAC), or like device.

A 12 bit analog to digital converter for VLSI applications in nuclear science

Abstract: A high-density monolithic analog-to-digital converter (ADC) has been designed and tested. The ADC features small silicon area and low power consumption for use in multichannel circuits for massively parallel particle physics detectors. The tested chip contains a linear ramp, precision high-speed comparators, a pipelined counter, and double buffering storage latches fabricated in a 2- mu m, two polysilicon CMOS technology. The prototype integrated circuit successfully combines digital frequencies in excess of 70 MHz with analog signals smaller than 1 mV. Test results show 1/4096 root-mean-square errors at conversion rates above 30 kHz, with less than 4 mW/channel power dissipation. >

Analog to digital converter

Abstract: A compact analog-to-digital converter (ADC) system suitable for high-resolution gamma-ray detectors has been developed around the Burr Brown PCM78P 16-b audio ADC. An associated application-specific integrated circuit (ASIC), handling four ADCs, provides sliding scale circuitry, lower threshold adjustment, channel number identification, and zero suppression. The conversion time is 4.5 mu s, and the differential nonlinearity, for 13-b resolution, is less than +or-0.8%. >

Method for using seismic data acquisition technology for acquisition of ground penetrating radar data

Abstract: A method and apparatus are used in the acquisition of data by ground-penetrating radar, wherein the signals thus obtained are input to a pre-amplifier which contains filtering component such as an anti-aliasing filter. The base gain of the system is switch selectable and electronically adjusted to bring the input signal to between one half and full scale on an analog to digital converter input. The converted digital value has a resolution of fifteen bits for processing.

Electronic watt-hour meter with selection of time base signals

Abstract: An electronic watthour meter is digitally configurable to operate as several different types of watthour meters for metering electrical energy from a variety of different electric utility services. Automatic scaling of line input currents is provided to scale the voltage input to an analog to digital converter over selected ranges such that low level and high level input signals are measured in an optimum range. A digital signal processor is employed to calculate values for metered electrical energy and output pulses, each proportional to a quantum of energy flowing in the circuit being metered. The processor calculates the value of DC offset errors inherent in the various analog circuits of the meter and uses that value in the calculation of metered electrical energy to compensate for such offset errors. The meter employs automatic and manually initiated test functions for testing the operation of the processor and other critical circuits in the meter.

Digital electronic still camera

Abstract: The camera is equipped to enable additional information such as an operation characteristic of the camera to be recorded into and reproduced from a removable record medium (16). A pickup image signal is picked up by a CCD image sensor (4,5) and converted into a digital signal by an analog to digital converter (9). The digital signal is temporarily stored into a digital memory (11) and written onto a removable optical disk apparatus (16). The digital electronic still camera further comprises an additional information recording and reproducing circuit (15) for recording and reproducing additional information such as an operation characteristic of the camera onto or from the optical disk apparatus.

Method and device for synchronizing on an outside event the sampling of measuring signals through a digitizing assembly of the oversampling type

Abstract: A digitalization assembly of the over-sampling type includes an analog to digital converter (2) producing at a frequency F=kf small-format p samples and a digital filter (3) which, through the summation of a certain number n of over-samples, produces validated larger P-format samples at the frequency f, at instants fixed by a clock. In order to readjust the sampling instants in relation to an outside event which can occur at any time, a temporary memory store (5) is inserted between the converter (2) and the filter (3) and, according to the instant of arrival of this event, the appropriate samples to be sent towards the filter for their summation are selected.

A pipelined 9-stage video-rate analog-to-digital converter

Abstract: The authors describe a nine-stage, pipelined, video-rate, analog-to-digital converter (ADC) in a 0.9- mu m CMOS technology. At a conversion rate of 20 Msamples/s, the converter has 10-b resolution, 56-dB signal-to-noise-and-distortion ratio (SNDR) with a 100-kHz input, and 54-dB SNDR with a 5-MHz input. It occupies 9.3 mm/sup 2/ and dissipates 300 mW. The key innovation in this ADC is the improved correction algorithm, which requires one fewer comparator per stage than used in traditional architectures. >

A/d (analog-to-digital) converter

Abstract: An A/D converter comprises a first stage integrator for receiving an input signal, a last stage integrator, a multibit A/D converter connected to the output terminal of the last stage integrator, an outer feedback loop connected between the output terminal of the multi-bit A/D converter and the input terminal of said first stage integrator and having a 1-bit D/A converter, an inner feedback loop connected between the output terminal of the multibit A/D converter and the input terminal of the last stage integrator and having a multibit D/A converter, and a digital signal processing circuit, connected to the output terminal of the A/D converter, for performing digital signal processing of an output from the A/D converter to eliminate quantization noise caused by the outer feedback loop.

Josephson counting analog-to-digital converter

Abstract: A superconductive analog-to-digital converter which uses a DC SQUID as a quantizer and a flip-flop counter as a digitizer has been designed, fabricated, and tested. The circuit was fabricated using a ten-level niobium process. Tests at 4.2 K demonstrated counting to the full 12-b accuracy of the design, monotonic A/D conversion with linearity to less than 1 LSB over the more than 9-b range of conversion, read-on-the-fly operation with counter overflow, and counter operation with a gate current bus.

Half-flash analog-to-digital converter using differential comparators and crossover switching

Abstract: A resistor-string divided into plural sets of unit-resistors generates plural reference voltages for the upper bits, while each divided set generates plural reference voltages for the lower bits. A first and second differential input are generated in direct and inverse proportion to the analog input voltage. Differential comparators for the upper bits compare two differential voltages from between the two reference voltages and the first and second differential input votlages. Two of the divided sets are selected according to the upper bit digital value and one reference voltage from each selected set is switched to a differential comparator for the lower order bits. Lower order bit comparison is similar to the high order comparison described above. Final digital value is obtained by linking the upper and lower bits digital value.

Superconducting sigma-delta analog-to-digital converter

Abstract: A superconducting sigma-delta analog-to-digital converter utilizes a superconducting inductor as the integrator and a Josephson junction connected in series between the inductor and ground as the quantizer. A SQUID generates sampling pulses at a selected GHz frequency which add to the inductor current flowing through the Josephson junction. When the combined current through the Josephson junction exceeds the critical current of the Josephson junction, a voltage pulse is generated which kicks back into the inductor to reduce the inductor current. The voltage across the Josephson junction is, therefore, a one bit digital representation of the analog signal. This one bit digital signal is converted to a multi-bit digital signal preferably by a decimator having superconducting circuits which reduce the frequency of the multi-bit digital signal to a frequency which can be further processed by semiconductor processors. Preferably, a weighting function is utilized in a conversion to improve accuracy.

A monolithic CMOS 20-b analog-to-digital converter

Abstract: The authors present a monolithic 20-b analog-to-digital converter (ADC) based on an oversampling feedback architecture. The converter consists of a time-continuous integrator at the input, a pulsewidth modulator in the forward branch of the loop (corresponding to a 10-b ADC), and a 1-b DAC (digital-to-analog converter) to generate the feedback voltage. The digital evaluation is carried out with a uniformly weighted rectangular window filter. The circuit is implemented in a standard 2- mu m CMOS n-well process and requires 14 mm/sup 2/ of silicon, including the pads. Measurement results are presented that demonstrate the feasibility of this architecture for 20-b accuracy. The complete circuit has a power consumption of 6.7 mW. >

High-speed, high-resolution analog to digital converter subranging architecture

Abstract: A very high-speed, high-resolution, low-noise, subranging analog-to-digital (AJD) converter architecture is described. It employs several sample-and-hold circuits in parallel. Also, the second-stage fine quantization flash A/D converter circuit of the conventional subranging A/D converter is replaced with a hybrid subranging converter of higher resolution and linearity. This is shown to achieve a very high dynamic range by minimizing noise due to the sample-and-hold and fine quantization circuits. This architecture permits construction of 16 to 18 bit 10 MHz A/D converters applicable for airborne radar systems.

Differential quantizer reference resistor ladder for use with an analog-to-digital converter

Abstract: An analog-to-digital converter employing a reference resistor ladder is disclosed for quantizing a differential analog input signal into quantization levels and converting each level into binary output code and requiring comparators having only two inputs. The converter receives positive and negative portions of a differential analog input signal. A first resistive network having a plurality of resistors of equal resistance spreads the negative input portion of the signal to thereby provide a plurality of comparison signals. A second resistive network, likewise having a plurality of resistors of equal resistance being coupled in series spreads the positive input portion of the signal to thereby provide a second plurality of comparison signals. A plurality of two-input comparators are provided to compare the comparison signals provided by the first resistive network with the comparison signals of the second resistive network. The comparator outputs are then encoded to thereby provide an N-bit binary output code response.

General purpose system for digitizing an analog signal

Abstract: A general purpose programmable optical analyzer employs a nonlinear gain at the input stage of an analog to digital converter in order to limit the number of bits used to resolve shot noise.

Cyclic analog-to-digital converter

Abstract: A cyclic analog-to-digital converter includes two arithmetic circuits and a single comparator. The output of each arithmetic circuit is connected to the input of the other arithmetic circuit. Each arithmetic circuit can modify the analog signal being converted in accordance with output signals from the comparator. Embodiments are disclosed in which the arithmetic circuits include switched capacitors and separate or shared operational amplifiers.

A Gray-code MOS current-mode analog-to-digital converter design

Abstract: A novel analog-to-digital converter (ADC) designed to operate without any clocking circuitry, such as a sample-and-hold, is described. The design presented is a first-generation Gray-code algorithmic converter (GA-ADC) with a continuous analog transfer function. The continuous transfer function results in a digital output that is Gray-coded. Performance degrades gracefully as the input exceeds the ADC's maximum sampling rate, enabling one to use a single ADC for a large variety of applications. In addition, the converter has other useful features such as low power dissipation, and high area efficiency. >

Automatic leak detector

Abstract: A method and apparatus are provided for automatically compensating for gain variations, component aging and drift characteristics of an associated circuit when trying to detect a leak. In the preferred embodiment an analog to digital converter will convert an analog signal from a sensor to a digital representation. A microprocessor will read the digital representation and compute the percentage change of the difference in values of the digital representations. Wherever the percentage change is greater than a threshold value, the microprocessor will activate an alarm to inform the user.

Toward a 62.5 MHz analog virtual pipeline integrated data acquisition system

Abstract: Requirements of analog pipeline memories at the SSC are reviewed and the concept of virtual pipelines is introduced. Design details and test results of several new custom analog and digital integrated circuits implementing sections of the virtual multiple pipeline (VMP) scheme are provided. These include serial, random access and simultaneous read and write random access analog storage and retrieval circuits, a 100 MHz systolic variable depth digital pipeline, and a prototype 32μs, 12 bit serial analog to digital converter.

Differential sensing current-steering analog-to-digital converter

Abstract: An analog-to-digital converter utilizes both a successive approximation register and a current steering circuit within a digital-to-analog converter to achieve an improved conversion speed, and improved resolution for a predetermined amount of power. The current steering circuit, which is controlled by the successive approximation register, connects constant current sources to current source loads to produce a differential signal output. By steering current from the differential current source loads to the constant current sources, a signal difference resolves at the output of the digital-to-analog converter faster and with greater resolution.

Technique for demodulating and decoding mls dpsk transmissions using a digital signal processor

Abstract: A system for demodulating and decoding differential phase shift keying (DPSK) transmissions utilizes a bandpass filter (11), an analog to digital converter (12) and a digital signal processor (13) Removal of the effects of unknown frequency component is achieved by applying a complex phase correction/rotation factor after DPSK demodulation The actual phase of the complex signal is never computed directly All of the processing from Rader decomposition (14) through carrier tracking filter is performed on the complex values and therefore requires only multiplication and addition operations which can be performed at high speed in a microcomputer or in dedicated arithmetic hardware

Time shift two-step analog to digital converter

Abstract: A method of and apparatus for high speed, high resolution, time-shift two-step analog-to-digital conversion (ADC) employing only one ADC module for both coarse and fine signal conversions. The same ADC module is used first for the coarse signal conversion with its output signal stored until the ADC completes the slower fine signal conversion to generate the conversion error for the subsequent compensation process. A digital signal is then generated after the two signals are processed by using a digital signal processing to compensate for conversion error.

Sample-and-hold droop compensator for high speed high resolution analog-to-digital converter

Abstract: A sample-and-hold droop compensation circuit including a ramp generator for producing a ramp signal synchronized with the hold timing of a sample-and-hold circuit and adjusted so as to tend to compensate the droop in the sample-and-hold output, circuitry for adding the ramp signal to the output of the sample-and-hold circuit to produce a sum signal, and a quantizer for providing a digital representation of the sum signal. The slope of the ramp signal is adjusted by a microcomputer by providing a reference input to the sample-and-hold circuit, determining the change in time of the sum signal, and adjusting the ramp signal so as to reduce the slope of the sum signal.