Showing papers on "Analog-to-digital converter published in 1994"

Digital television system

Abstract: A digital television system (10) is provided. System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into separate video signals by composite video interface and separation circuit (16). The separate video signals are converted to digital video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c).

Sigma-delta analog-to-digital converter with filtration having controlled pole-zero locations, and apparatus therefor

Abstract: A sigma-delta (ΣΔ) analog-to-digital converter (ADC) accepts band-limited analog signals, and subtracts an analog replica of an output pulse- or amplitude-density modulated (ADM) signal therefrom to produce an error signal. The error signal is processed by an analog filter or resonator with a nondelayed forward path and a tapped nonaccumulating delay line, and summed feedback and feedforward weights coupled to the taps, to thereby produce a resonated signal. An ADC processes the resonated signal, and produces the ADM signal. The ADC undesirably produces quantization noise. A digital-to-analog converter (DAC) noiselessly converts the PDM signal into the analog replica, to aid in forming the error signal. In a particular embodiment of the invention, the resonator includes a recursive analog transversal filter with delays and linear weighting elements for linearity and high operating speed. The ADC may be in a high-speed system such as a radar.

Sub-ranging analog-to-digital converter

Abstract: The present invention provides a sub-ranging analog-to-digital (A/D) converter (10) with improved speed and power consumption characteristics relative to known sub-ranging converters. The sub-ranging A/D converter utilizes information relating to the values of the bits determined in one stage (12) to define the range of operation for a subsequent stage (14). In one embodiment, the subsequent stage utilizes three-input comparators (48) in determining the value of bit. Two of the inputs are used to receive signals representative of the upper and lower limits of the range of operation that has been determined by the prior stage and the other input is used to receive the analog signal (18). The three-input comparator operates to produce an output signal that is indicative of the relationship of the analog signal to a threshold level within the defined range of operation determined by the prior stage.

Digitally self-calibrating pipeline analog-to-digital converter

Abstract: A self-calibrating pipeline analog-to-digital converter having a plurality of analog-to-digital conversion units and including a recursive calibrating section operable for calibrating errors associated with an immediately preceding first conversion unit. The recursive calibrating section includes circuitry for receiving an analog output signal generated from said first conversion unit in response to an analog input signal provided to the first conversion unit; circuitry for receiving a digital output signal generated from the first conversion unit in response to a digital input signal provided to the first conversion unit; circuitry for generating a conversion signal corresponding to a quantized representation of the analog output signal; and circuitry for generating a calibration signal having a value equal to the conversion signal in response to the digital input signal being a first digital value and having a value equal to the sum of the conversion signal and a calibration value in response to the digital input signal being a second digital value.

Pipelined multi-stage analog-to-digital converter

Abstract: A pipelined multi-stage analog-to-digital converter (ADC) exhibits high speed and high resolution characteristics in a small chip area using a CMOS process. An optimized high resolution multi-stage ADC improves integral non-linearity errors (INL) and differential non-linearity (DNL) errors and hence increases yield. A binary-weighted capacitor array is used in a multiplying digital-to-analog converter (MDAC) in a front-end stage, and a unit capacitor array is used in the MDACs of the latter stages thereof. Offset, feedthrough and gain errors are removed via digital correction. A digital calibration technique is adopted to reduce the non-ideal effects resulting from component mismatch, by measuring all the code errors of the front-end stage, to thereby minimize the midpoint code DNL error without reference to code symmetry.

Apparatus and method for sampling signals synchronous with analog to digital converter

Abstract: This invention provides various methods and techniques for providing a synchronous programming of a microcontroller and its associated analog to digital converter for a maximum rate of taking digital samples of alternating current analog signals which techniques are selectively combined to provide microcontroller based controls and protective relays such as for use with electric utilities.

Analog-to-digital converter technology comparison

Abstract: Analog-to-digital converters are ubiquitous, critical components of signal processing systems. This presentation surveys the state-of-the-art for ADCs and includes both experimental converters and commercially available parts. The shape of the distribution on a resolution vs. sampling rate graph provides insight into ADC performance limitations. For sampling frequencies ranging from /spl sim/0.5 MSPS to /spl sim/4 GSPS, resolution falls off by /spl sim/1 bit for every doubling of the sampling rate. This effect can be related to aperture jitter. For ADCs operating at /spl ges/4 GSPS, the speed of the device technology is a limiting factor. In order to push back these limits, many ADC architectures have been proposed and implemented.

Two dimensional detector array for CT scanners

Abstract: A CT scanner (10) includes a reconstruction processor (82) for reconstructing an image from digital signals from detector arrays (20). Each detector array includes scintillation crystals (22) arranged in an array for converting x-ray radiation into visible light. An array of photodetectors (24) is mounted beneath the scintillation crystal array for converting light emitted from the scintillation crystals into electrical charge. The combination scintillation crystal, photodetector array is mounted to and preferably integral with an integrated circuit (26) having charge storage devices (32, 34). Electrical charge generated by each photodetector is integrated and stored alternately by a corresponding pair of charge storage devices. The charge storage devices operate as a double buffer in which one charge storage device accumulates charge while the other holds an accumulated charge until read out by downstream circuitry. The downstream circuitry includes a plurality of amplifiers (66) and an analog digital converter (62) integrally formed on the substrate. The analog to digital converter converts analog signals corresponding to the stored charges into digital values. The digital valves created on the detector arrays are transferred in digital form to the reconstruction processor.

High-resolution encoding process for an integrated optical analog-to-digital converter

Abstract: A technique is described for extending the resolution of an integrated optical multi-interferometer guided-wave analog-to-digital converter. The optical output waveform for each interferometer is symmetrically folded at twice a proper modulus. A small comparator ladder mid-level quantizes each interferometer's detected output to encode the analog signal in a symmetrical number system (SNS) format. By incorporating the SNS encoding, resolution greater than 1 bit per interferometer can be provided. Analog signal levels that can cause possible encoding errors are examined and their impact on the overall amplitude analyzing function is discussed. The maximum laser pulse width and maximum fluctuation in the sampling interval that can be tolerated is also discussed. Results indicate that 11-bit resolution can be provided with three interferometers and 39 comparators.

Data detection methods and apparatus for a direct access storage device

Abstract: A method and apparatus are provided for maximum-likelihood data detection in a partial-response (PR) data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples. A plurality of digital samples are received from the ADC. The received digital samples are applied to a selected first filter and a selected second filter. The first filtered digital samples are applied to a first data detector, and the second filtered digital samples are applied to a second data detector. A predetermined parameter is identified, and at least one of the first and second data detectors is selected responsive to the identified predetermined parameter.

Dithered analog-to-digital converter

Abstract: A dithered analog-to-digital converter includes a correlator to detect dither residue in the output signal. The correlator output is accumulated and used in a feedback loop to control the gain of the dither signal so as to null the residue. Problems associated with the low bandwidth of the feedback loop, and corruption of the accumulator value due to overload, are addressed by provision of a preload register from which the accumulator is initialized on power-up and on detection of an overload. This approach provides quick settling time and avoids statistical anomalies associated with decimation approaches to overload.

Sigma Delta analog to digital converter with three point calibration apparatus and method

Abstract: An analog to digital converter 10 has a switched capacitor analog modulator 12 with three point calibration. Offset calibration applies on offset correction value in OCR 22 to an uncalibrated digital output. Register 28 holds a desired full scale value, register 24 holds a positive full scale value, and register 26 holds a negative full scale value. Depending upon the polarity of the converted analog signal, the offset corrected digital signal is multiplied by a positive or a negative gain correction factor.

Doppler bandwidth dependent estimation of a communications channel

Abstract: A device and method of adjusting an equalizer in a digital communications receiver in response to relative velocity between the communications receiver and a communications transmitter. A radio frequency receiver receives a radio frequency signal from the communications transmitter through a communications channel, and an analog to digital converter digitizes a first portion of the radio frequency signal during a first time period, and generates a first data signal made up of digital samples. The analog to digital converter also digitizes a second portion of the radio frequency signal during a second time period and generates a second data signal, also made up of samples. A channel estimator estimates characteristics of the communications channel in response to a portion of the first data signal, and generates a first channel estimate in response thereto. Finally, a processor determines an estimated velocity of the communications receiver relative to the communications transmitter, weights the first channel estimate in response to the estimated velocity, and generates a revised channel estimate in response to the weighting of the first channel estimate and the second data signal.

Multiple channel analog to digital converter

Abstract: A multiple channel analog to digital converter utilizing common conversion circuitry for converting multiple analog signals into corresponding digital signals. The converter includes an input stage having a plurality of capacitors, each one corresponding to one of the analog signals. The capacitors sample the respective analog signals and are successively coupled to common conversion circuitry, including a CDAC and a comparator. The CDAC iteratively increments or decrements the voltage of a selected one of the sampled analog signals for comparison to a reference voltage by the comparator. The comparator output is latched by a successive approximation register to provide a parallel output signal which is fed back to control the CDAC.

Copyright protection for digital signal recording and/or reproduction and recording medium thereof

Abstract: A digital image signal recording and/or reproduction method and/or apparatus by which a copyright protection signal employed by a software tape for use with an analog video tape recorder can be recorded and/or reproduced with a digital video tape recorder of the compression type. When a copyright protection signal detection circuit detects a disturbing signal inserted in a video signal, an output of an analog to digital converter is stored into a memory. An H counter supplies a line number upon detection of the disturbing signal as LINES data to a line pack processing microcomputer. The data of the memory are supplied as line data to the line pack processing microcomputer under the switching control of a switching circuit. Using the received data, the line pack processing microcomputer produces pack data and sends the pack data to a format converter of a digital video tape recorder.

Precision analog-to-digital converter with low-resolution and high-resolution conversion paths

Abstract: An analog-to-digital converter utilizes low-resolution and high-resolution conversion paths for precision voltage measurements. A first conversion made using a comparatively low resolution ADC is used to predict the reference voltage to one input of a null detector that receives the input voltage on another input, and effectively magnifies the voltage difference between its inputs. In a preferred embodiment, the duty cycle of a pulse-width modulator is adjusted to precisely adjust the reference voltage to provide a nulled (or near null) reading from the null detector. A low resolution ADC then converts the voltage from the null detector, which when added to the reference voltage, yields a final reading with 18-bit to 22-bit accuracy. The preferred embodiment is implemented to read the output from a pressure transducer and employs a binary search technique to rapidly adjust the duty cycle of the pulse-width modulator. The system utilizes a single ADC which is multiplexed between the low-resolution, high-speed reading and high-resolution, low-speed reading of the fully settled output of the null detector.

Pipelined analog-to-digital converter with curvefit digital correction

Abstract: An ADC system in which raw ADC data is received and digitally manipulated to increase the accuracy of the resultant digital output word. In one embodiment, the digital manipulation of this invention is performed on data which has been preliminarily adjusted for errors caused by use of an interstage gain less than ideal. In one embodiment, digital correction is performed based only on the errors of a plurality of most significant bit stages, rather than all stages, as the effect on error of the digital output word is of decreasing importance for stages of less significance. In accordance with one embodiment of this invention, offset error and full scale error are determined by applying ±Vref as an input signal to the ADC. These values allow the raw digital data from the ADC to be compensated in either hardware or software to provide a more accurate digital representation of the analog input voltage being measured. In accordance with another embodiment of this invention, second order errors are removed by determining the magnitude of, par example, capacitor value voltage coefficients of the MSB stage of the ADC after calibration of lesser significant bit stages, and using these voltage coefficients to further adjust the digital output word, providing an even more accurate digital representation of the analog input signal being mesured.

Development and testing of a flash analog-to-digital converter based system for pulse shape discrimination of nuclear radiation pulses

Abstract: A digital signal processor (DSP) based system is under development for analyzing and processing pulses produced by radiation detectors. The system is designed to replace conventional pulse-type, analog-to-digital converters. It is capable of capturing the complete radiation induced pulse in digital form. Subsequently, all the pulse features can be analyzed digitally (e.g., pulse validation, energy information, dynamic threshold determination, pulse duration, pulse shape analysis, and noise reduction). A prototype system has been built and performance parameters have been evaluated. >

Analog-to-digital converter and reference voltage circuitry

Abstract: The analog to digital converter 300 has voltage reference circuitry 326 which includes a bandgap generator and a correction circuit 5300. The bandgap generator includes first and second NPN transistors 5211-5224, 5231-5232 of differing emitter areas and an operational amplifier 5202 with inputs sensing the collector current of the first and second NPN transistors 5211-5224, 5231-5232. First and second NPN transistors 5211-5224, 5231-5232 have their bases tied together. The output of the amplifier 5202 drives the bases of the NPN transistors 5211-5224, 5231-5232 through a resistor divider 5251-5253.

Two-step subranging analog-to-digital converter

Abstract: A subranging analog-to-digital converter wherein, during a first phase, a differential analog input voltage is held by a track and hold circuit and is fed to a low resolution flash ADC to provide the most significant bits (MSBs). During a second or recirculating phase, flash ADC output segments corresponding to the MSBs are fed to respective current switches of a current DAC to produce complementary analog conversion currents that are coupled to the track and hold circuit. In response to the complementary DAC currents, the output stage of the track and hold circuit is used to subtract a voltage corresponding to the MSBs from the input voltage without the use of a separate subtractor. Further, the DAC current switches provide equal currents during the first or MSB phase to deactivate the subtraction function during the first phase.

16-channel oversampled analog-to-digital converter

Abstract: Oversampled analog-to-digital conversion has been demonstrated to be an effective technique for high resolution analog-to-digital (A/D) conversion that is tolerant to process imperfections. The area and power budget of conventionally designed oversampled analog-to-digital converters has precluded their application from areas where a large number of low frequency signals need to be converted simultaneously. A new oversampled A/D design methodology is proposed to cut the area and power budget per channel of an oversampled analog-to-digital converter. The design and implementation of a 16-channel oversampled analog-to-digital converter is presented which can be used as the core of the multichannel data acquisition system. The prototype achieved 80 dB of signal-to-noise-plus-distortion over 1 kHz, -80 dB of crosstalk and used less than 20 mW of power excluding clock generation. >

Digital filter and oversampling analog to digital converter employing the same

Abstract: A digital filter has a cut-off frequency which can be varied by a simple control circuit. The digital filter includes a tap coefficient setting section and a convolution calculation section. The convolution calculation section is constructed so as to repetitively perform the processing of first performing repetitive convolution calculation wherein a same convolution calculation operation is performed once or successively by a plurality of times using same tap coefficients or same input data and then varying the tap coefficient or the input data to allow the repetitive convolution calculation to be repeated subsequently. The digital filter can be applied to an oversampling analog to digital converter.

Analog to digital converter providing varying digital resolution

Abstract: An analog to digital converter which includes a resistive network for generating a number of first reference voltages related to each other by a first linear relationship and a number of second reference voltages related to each other by a second linear relationship, where the first linear relationship is different from the second linear relationship. Also included are first comparators which compare an analog signal to each one of the first reference voltages to produce specified first comparator signals where a respective comparator of the first comparators is provided for each of the first reference voltages. Second comparators are provided to compare the analog signal to each of the second reference voltages to produce second comparator signals where a respective comparator of the second comparators is provided for each one of the second reference voltages. Also included is an encoder to directly convert the first comparator signals and the second comparator signals to a linear digital encoded signal having respecting different quantization resolutions in different parts of its range.

Low-power current-mode algorithmic ADC

Abstract: A low-power (2.5 V) current-mode analog to digital converter suitable for mobile radio transceiver application is presented. It uses current injection technique to increase the speed of current mirrors. The 4-bit ADC is implemented in 1.2 /spl mu/m CMOS technology. It has a conversion rate of 4.5 MHz, a power dissipation of 0.5 mW and an active chip area of 0.02 mm/sup 2/. >

A mismatch independent DNL-pipelined analog to digital converter

Abstract: A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes, the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be-realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 /spl mu/m CMOS process show that 3.3 MSamples/s can be resolved at 20 mW per bit. >

n-bit analog-to-digital converter with n-1 magnitude amplifiers and n comparators

Abstract: A serial-type A/D converter uses magnitude amplifiers("magamps") and comparators for effecting the conversion of analog signals to Gray scale code signals that are then converted to binary digital signals by a Gray scale code-to-binary portion of the serial-type A/D converter. More specifically, a serial-type A/D converter uses an n-bit converter that has n-1 magamps and n-comparators. The n-1 magamps are cascaded such that the V OL and V OH outputs of a stage are the inputs to the next stage. The output of the comparators are input to the Gray scale code-to-binary portion of the serial A/D converter. The latching of the comparators occurs outside of the magamps. This allows for the parallel latching of the n comparators. The speed of the serial-type A/D converter is determined by the bandwidth of the magamps. The serial-type A/D converter includes an offset method that significantly reduces the effects of early voltage, V A , on the output waveforms. Each stage of the serial-type A/D converter may have any desired gain and not limited to a particular gain.

A low power 20 bit instrumentation delta-sigma ADC

Abstract: A very low power, high resolution analog to digital converter has been developed for instrumentation applications. User selectable 16 bit and 20 bit outputs are available. Employing a 4th order delta sigma modulator, the ADC achieves a DNL of less than /spl plusmn/0.5 LSB of 20 bits. Measured S/(D+N) is over 105 dB. The 10.8 mm/sup 2/ die consumes less than 2 mW from a single 5 V supply and is implemented in a 1.2 /spl mu/m p-well CMOS technology. >

Multiple slope analog-to-digital converter having increased linearity

Abstract: A multiple slope integrating analog-to-digital converter (ADC) includes an integrator and a comparator in which an input voltage to be measured is applied to a summing node at the input of the integrator during an integrate cycle, while at the same time positive and negative reference currents are selectively applied to the summing node by a controller which monitors the output of the comparator in order to come as close as possible to nulling the voltage magnitude at the output of the integrator. A controller keeps track of the charge that has been added to and removed from the integrator during the integrate cycle, and provides a coarse conversion value. The residual voltage is de-integrated to provide a fine conversion value, which is added to the coarse conversion value to provide a final value. The switches which control selection of the positive and negative reference currents are implemented and operated in such a way that linear error due to current injected into the integrator is minimized, and increased conversion speed is exhibited. At any given time during the integrate cycle, only one switch at a time is ON.

Vibration type gyroscope apparatus

Abstract: A vibration type gyroscope apparatus of digital type which is good in operability and high in detection accuracy includes a variable gain amplifier (3), for amplifying a detection signal of a vibration type gyroscope, and an analog to digital converter (5), for converting an output signal of the variable gain amplifier (3) into a digital signal, are integratedly contained in the vibration type gyroscope apparatus. Accordingly, the detection signal is amplified and converted into a digital signal at a range as near as possible to a vibration type gyroscope (1) to thereby prevent the detection signal from being deteriorated by the influence of external noise in a transmission line. Accordingly, the transmission line can be used effectively, so that the signal can be transmitted at high-grade and high-fidelity.

Flash analog-to-digital converter and method of operation

Abstract: A flash analog-to-digital converter (8) is provided which includes a comparator array (10) which provides a thermometer code output THC1 through THC7. A binary search encoder (12) is coupled to the comparator array (8) as shown, and provides a binary code output B2 through B0.