Showing papers on "Analog-to-digital converter published in 2022"
01 Apr 2022
TL;DR: In this article , the authors comprehensively investigated analog-to-digital converter (ADC) design for compute-in-memory array and showed that 6-bit ADC precision is sufficient to guarantee no loss of accuracy for large arrays, while achieving the best tradeoff between hardware performance and area overhead.
Abstract: This article comprehensively investigates analog-to-digital converter (ADC) design for compute-in-memory array. The authors show that 6-bit ADC precision is sufficient to guarantee no loss of accuracy for large arrays, while achieving the best tradeoff between hardware performance and area overhead, compared to prior state-of-the-art designs.
10 citations
TL;DR: The architecture and performance of ADC for UIS, including successive approximation register (SAR), sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced.
Abstract: As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. The performance of integrated circuits (ICs) in portable UIS obviously affects the effectiveness and quality of ultrasonic imaging. In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital signal processing (DSP) or microcontroller unit (MCU). The accuracy and speed of the ADC determine the precision and efficiency of UIS. Therefore, it is necessary to systematically review and summarize the characteristics of different types of ADCs for UIS, which can provide valuable guidance to design and fabricate high-performance ADC for miniaturized high resolution UIS. In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced. In addition, comparisons and discussions of different types of ADCs are presented. Finally, this paper is summarized, and presents the challenges and prospects of ADC ICs for miniaturized high resolution UIS.
10 citations
28 Apr 2022
TL;DR: The low power consumption values suggest the use of proposed flash analog to digital converter in designing next generation of portable, handheld and energy efficient low power electronic devices that are compatible with IoT technologies.
Abstract: The design and development of low power electronics has garnered a lot of interest in the recent past due to rise of Internet of Things. The majority of IoT enabled devices rely on reliable data mining and data handling techniques that process both analog and digital data. The present manuscript focusses on the design of an ultra-low power 2- bit flash analog to digital converter. The flash analog to digital converter is implemented using a modified double-tail latch type comparator that consumes a minimal power of 0.65 µW and a delay of 133ps for an operational voltage of 0.6V at 16m technological node. The proposed analog to digital converter is equipped with bubble error correction and digital encoding techniques for fast and reliable data conversion. The proposed analog to digital converter consumes a power of 0.4 mW at the lowest operational voltage of 0.6V for 16nm technological node. The simulation of the proposed flash analog to digital converter yields a sub-milliwatt power consumption at different operational voltage ranging from 0.6V to 1.2V. The low power consumption values suggest the use of proposed flash analog to digital converter in designing next generation of portable, handheld and energy efficient low power electronic devices that are compatible with IoT technologies.
4 citations
TL;DR: In this paper , an ultra-low power small footprint integrated 3-bit all optical analog to digital (AO-ADC) with no missing code has been presented, which is made possible using PhC-SOA instead of conventional SOA.
Abstract: • An ultra-low power small footprint integrated 3-bit all optical analog to digital is presented. • Designing 3-bit AO-ADC with no missing code has been made possible using PhC-SOA instead of conventional SOA. • An innovative encoder is proposed to produce binary code at the output. • The structure parameters are optimized by microfluidic infiltration which is a post-fabrication fine tuning method. Integrating a photonic crystal based semiconductor optical amplifier (PhC-SOA) composed of InP/InGaAsP/InP heterostructure with eight PhC based channel drop filters (CDFs) based on an InGaAsP platform, we have designed a fully integrated all-optical 3-bit analog to digital converter (AO-ADC). A probe signal after passing through a 9-µm long PhC-SOA in the presence of an amplitude-modulated Gaussian pulse of 1.422 ps width and maximum energy of 37.2 fJ exhibited a 4.8-nm wavelength shift. The eight appropriately designed PhC-CDFs have coded the chirped signal into eight quantization levels. The numerical results show that the proposed structure can convert analog photonic signals into 3-bit digital output with no missing code at 10Gs/s. The proposed AO-ADC structure with a small footprint of 455 μm 2 , along with its ultra-low power consumption, can pave the way for the further development of the next-generation integrated photonic chips.
4 citations
TL;DR: In this paper , a cross-coupling input technique is proposed to select the direction of input coupling according to the signal polarity, which can greatly improve the speed of quantization.
4 citations
TL;DR: The test results prove the effectiveness of this method for generating high-resolution ADC test signals based on the principle of time-alternating sampling and explain its method, analyzes its error and proposes a digital pre-processing method to reduce the error.
Abstract: In the high-resolution analog circuit, the performance of chips is an important part. The performance of the chips needs to be determined by testing. According to the test requirements, stimulus signal with better quality and performance is necessary. The main research direction is how to generate high-resolution and high-speed analog signal when there is no suitable high-resolution and high-speed digital-to-analog converter (DAC) chip available. In this paper, we take the high-resolution analog-to-digital converter (ADC) chips test as an example; this article uses high-resolution DAC chips and multiplexers to generate high-resolution high-speed signals that can be used for testing high-resolution ADC chips based on the principle of time-alternating sampling. This article explains its method, analyzes its error and proposes a digital pre-processing method to reduce the error. Finally, the actual circuit is designed, and the method is verified on the circuit. The test results prove the effectiveness of this method for generating high-resolution ADC test signals.
3 citations
TL;DR: In this paper , the authors proposed an efficient digitizer for low-current measurement (D-LCM) which provides a digital output proportional to the sensed current, with reduced quantization error of the analog-to-digital converter (ADC).
Abstract: This article proposes an efficient digitizer for the measurement of low currents over a wide span. The proposed digitizer for low-current measurement (D-LCM) technique provides a digital output proportional to the sensed current, with reduced quantization error of the analog-to-digital converter (ADC). In addition, the proposed D-LCM technique ensures the following features: 1) simple and cost-effective architecture for current-output sensors; 2) bidirectional current sensing over a large span for a unipolar ADC; and 3) reduced effects of various error sources. The novel D-LCM design, comprising a transimpedance amplifier and a multiregime integrator, helps to realize the aforementioned features. The analog circuitry is intelligently controlled by a simple digital unit such that the input span is split using a geometric-mean approach and operated in multiple regimes. The entire methodology and its circuit realization are mathematically derived, and its capability to reduce the effects of the ADC quantization errors is discussed. Detailed evaluation of other error sources and necessary compensation/design guidelines are also elaborated. The performance of the D-LCM technique is evaluated using simulation studies and experimental tests on a developed hardware prototype. Experimental tests demonstrate that the dual-regime-based D-LCM technique acts as a digitizer for the current range tested (i.e., −100 nA to 100 nA) with a nonlinearity error of 1.3%. It is also shown that the error could be reduced to around 0.47% using a triple-regime-based D-LCM technique. The precision-related performance of the D-LCM is also experimentally obtained and shown to be adequate. The developed D-LCM technique is useful for many instruments, such as retarding potential analyzers (RPAs) and photodiode-based systems. The proposed technique was implemented and verified in an RPA flight prototype used for the study of Earth’s ionosphere.
2 citations
TL;DR: In this paper , a new successive approximation register (SAR) analog-to-digital converter (ADC) search methodology was proposed for low-activity signals for reducing comparator activity and switching energy of DAC.
Abstract: Low-activity signals, such as voice, electrocardiogram (ECG), and ultrasonic signals, in the Internet-of-Things applications have both posed unique challenges and offered special opportunities for modern analog-to-digital conversion. This article presents a new successive approximation register (SAR) analog-to-digital converter (ADC) search methodology, which is aimed at low-activity signals for reducing comparator activity and switching energy of digital-to-analog converter (DAC). By using statistical histogram information of the low-activity signals, two search solutions are proposed. The first solution is designed for some part of signal that has small difference between two adjacent samples, while the second solution is designed for that with large difference. To engage one suitable solution, the digital interval between two adjacent samples needs to be detected. In addition, a new DAC tactic is proposed to reduce the activity of DAC switches. Our simulated 10-bit SAR ADC for voice signals shows that by using our proposed method, the comparator activity is reduced by 62.09%, and the DAC switching energy is decreased by 85.90% compared to the monotonic method. In addition, the activity of DAC switches is further trimmed by 39.66% compared to the monotonic method.
2 citations
TL;DR: In this article , a two-step coarse-fine time-to-digital converter (TDC) is fabricated in 65-nm CMOS, with a relaxation oscillator based peak counter (ROC) for the coarse stage and a successive approximation ADC for the fine stage.
Abstract: A novel two-step coarse-fine time-to-digital converter (TDC) is fabricated in 65-nm CMOS, with a relaxation oscillator based peak counter (ROC) for the coarse stage and a successive approximation analog-to-digital converter (SAR-ADC) for the fine stage. A reconfigurable 3-bit digital counter expands the dynamic range, and a high-precision 9-bit SAR-ADC ensures the resolution. The proposed ROC-ADC scheme conducts the time residence and the transfer linearity well for two-step quantization. Experimental results show that the presented 12-bit TDC achieves a high resolution less than 8 ps and a wide dynamic range up to 30 ns, with the differential nonlinearity (DNL) and integral nonlinearity (INL) values of 0.92 LSB and 1.07 LSB, respectively. The TDC consumes a low power of 0.6 mW from a 1-V supply, with the active area of 0.14 mm2.
1 citations
TL;DR: In this paper , the authors proposed a low power 10-bit asynchronous fully-differential column analog to digital converter (ADC) with successive approximation (SAR) and charge redistribution in a 180 nm SoI technology.
Abstract: Abstract This paper proposes a low power 10-bit asynchronous fully-differential column analog to digital converter (ADC) with successive approximation (SAR) and charge redistribution in a 180 nm SoI technology. The ADC is designed for use in Spacepix-2 monolithic active pixel sensor. A novel folded architecture of internal capacitive digital to analog converter (CDAC) is proposed. The total capacitance of CDAC is 512 fF, with a single unit capacitor capacitance only 0.5 fF and a size of 2.5 × 1.4 μm 2 . The total input capacitance of the proposed column ADC is only 220 fF. Two columns of a pixel matrix share a single ADC to double layout width. The layout area is 120 × 923 μm 2 . The sample rate is 4 MSps with power consumption of 225 μW from 1.8 V power supply.
1 citations
26 Feb 2022
TL;DR: In this article , the design of comparator simulated at 90nm and 45nm CMOS technology has reduced the overall power consumption of SAR-ADC, which can be used for all electronic implant devices without affecting the performance of SARADC.
Abstract: In modern expertise inventions the essential growth has been observed in electronic sectors. All the electronic devices work on the signals that can be either analog or digital. With the advancement in CMOS technologies, IC’s were designed that can be used in electronic systems, where the major concern was power consumption without affecting the performance of the device. One of the vital blocks in this system is analog-digital converter (ADC) that acts as interface amid the analog worlds to the digital world. Among the prevailing ADC architectures, one of the utmost used is successive approximation register. SAR based ADC achieves an improved sampling rate at low power and high speed. It is appropriate for data acquisition and provides a worthy trade-off amongst design complexity and power dissipation by providing high-energy efficiency. In SAR-ADC architectures, one of the vital blocks that consume much amount of power is comparator. This paper converses the design of comparator simulated at 90nm and 45nm CMOS technology that has reduced the overall power consumption of SAR-ADC. Finally, it concludes the appropriate method that can be utilized to accomplish ultra-low power consumption and can be used for all electronic implant devices without affecting the performance of SAR-ADC.
TL;DR: In this article , the authors present a comparison between the different designs in the literature for both the ring and cavity resonators using the RSOFT simulator followed by the challenges and some novel trends.
Abstract: — This paper reviews all-optical analog to digital converters (OADCs) based on the photonic crystal. They are nonlinear applications and are used in all-optical data processing systems. They are consisting of one input (i.e., continuous analog optical signal) and two or five outputs (i.e., binary code). Most of these structures have two operation steps. The first one is a nonlinear demultiplexer followed by second stage that has an optical coder. The demultiplexer creates the discrete levels for the continuous optical input signal; then the optical coder generates output bits. There are two techniques to design OADC, ring and cavity resonators. All OADCs structures use the finite difference time domain (FDTD) and plane wave expansion (PWE) analysis methods. The paper presents a comparison between the different designs in the literature for both the ring and cavity resonators using the RSOFT simulator followed by the challenges and some novel trends.
TL;DR: In this paper , a low power and low noise digital pixel sensor (DPS) is presented, where a novel simulation method called transient-based AC noise simulation (TBAS) is used to estimate the noise components of the lowpowered single-slope (SS) analog-to-digital converter (ADC).
Abstract: A Low-power and low-noise digital pixel sensor (DPS) is presented in this paper. To design and analyze the random noise (RN) of the developed DPS, especially, we utilize a novel simulationmethod called transient-based AC noise simulation (TBAS) which can effectively help to estimate the noise components of the lowpowered single-slope (SS) analog-to-digital converter (ADC). Based on this noise analysis, the high performance DPS has been successfully designed and demonstrated.
01 Jan 2022
TL;DR: In this paper , a high-speed latch comparator has been designed for the application of analog to digital converter (ADC) and the circuit's speed has been improved by a proposed comparator.
Abstract: In this paper, high-speed latch comparator has been designed for the application of analog to digital converter (ADC). The circuit’s speed has been improved by a proposed comparator. It is designed with a supply voltage of 3.3 V at 180 nm CMOS technology at Cadence Virtuoso. By using the differential amplifier and latch design, a complete design for comparator is obtained.
21 Dec 2022
TL;DR: In this paper , the authors proposed a design of SAR ADC for a decentralised merging unit, a small unit which will be installed in the CT base, and this will directly give a digital output that complies with IEC 61850.
Abstract: Evolution in technology in substation automation provides engineers with numerous new challenges. These advancements in technology are defined in the IEC 61850 standard. This standard depicts the communication mapping for substation automation. The primary problem is to switch out outdated protective relays with reliable, newly developed microprocessor-based relays. These are called intelligent electronic devices (IEDs) in the automation field. The analog to digital converter is a crucial merging unit (MU) component. In order to meet the application of the requirements, an analog signal with an input frequency of 50 Hz, a current of 0 to 2 amps, and a voltage of 0 to 5 volts into a digital format with a high resolution of 14 to 16 bits. In the current scenario, the merging unit is placed near the substation where relay control panels are located. This merging unit takes analog signal from the CT through the cables which are running from the CT to the merger unit control box. This paper proposes a design of SAR ADC for a decentralised merging unit, a small unit which will be installed in the CT base. Furthermore, this will directly give a digital output that complies with IEC 61850. An optical fibre will send that signal directly by a wired or wireless control system.
TL;DR: In this article , the relationship between the phenomenon of self-heating and power consumption in integrated circuits is studied. And a low power analog-to-digital converter is used as an example.
Abstract: The relationship between the phenomenon of self-heating and power consumption in
integrated circuits is studied. A low power analog-to-digital converter is used as an
example. The improvement in self-heating effects has been demonstrated for the converter.
01 Jan 2022
12 Oct 2022
TL;DR: In this paper , a second order discrete-time sigma delta analog-to-digital converter (ADC) is presented for integration within an audio application, the input bandwidth being 25kHz.
Abstract: This paper aims to present the design of a second order discrete-time sigma delta analog to digital converter (ADC). This converter is intended for integration within an audio application, the input bandwidth being 25kHz. The article also provides details regarding the stability of second and third order modulators. The converter implemented in 180nm achieves a SNR of 87.25dB, for a 5V supply voltage, with a sampling rate of 12.8MHz and oversampling ratio (OSR) of 256, and consumes 3.81mW.
16 May 2022
TL;DR: In this article , a hybrid successive subtraction method of analog to digital converter (HSSADC) was proposed to exploit the advantages of both the schemes and overcomes the shortcomings of both methods.
Abstract: Two techniques of successive subtraction type of analog to digital converter (SSADC) topology, one that uses N-different reference voltages for an N-bit SSADC (NR SSADC) and the other with just one reference voltage (OR SSADC), are analyzed to identify the shortcomings in the methods. A novel hybrid successive subtraction method of analog to digital converter (HSSADC) that exploits the advantages of both the schemes and overcomes the shortcomings of both methods is presented here. The proposed HSSADC technique is analyzed and studied through simulation. The simulation results validate that the proffered HSSADC technique provides better performance than either the NR SSADC or OR SSADC, especially at higher resolution. The proffered HSSADC is compared with existing techniques.
TL;DR: A new design of low-power and fast analog to digital converter is presented and the suggested approach for rereading the image for limited number of pixels was designed and simulated, showing a considerable power decrease compared to the suggested state that depends on the pixel values.
Abstract: Analog to digital converters (ADCs) enable the processing of real-world analog signals in the digital realm. These converters are widely used in sensor systems, medical components, multimedia systems, image sensors, and wireless sensor nodes. Today, in portable devices that are powered by batteries, low power consumption and small area are a major and important need. Therefore, methods that can reduce power consumption and area have a variety of applications and are of great importance. Power consumption is one of the most important features of an integrated analog to digital converter. In this paper, a new design of low-power and fast analog to digital converter is presented. This design is used for specific applications for image processing. The suggested approach for rereading the image for limited number of pixels was designed and simulated, showing a considerable power decrease compared to the suggested state that depends on the pixel values.
22 Jul 2022
TL;DR: In this article , a tunnel field effect transistor (TFET)-based flash analog-to-digital converter (ADC) was implemented using 20 nm TFET technology to achieve satisfactory performance with lower power dissipation.
Abstract: This chapter presents a tunnel field effect transistor (TFET)-based flash analog-to-digital converter (ADC). All the fundamental blocks of the flash ADC are successfully implemented using TFET. The goal of this chapter is to demonstrate satisfactory performance of flash ADC with low power dissipation. As the world depends on wireless communication extensively, there is a need for an ADC having smaller delay, lower power dissipation, and high sampling frequency. All of the naturally occurring signals are analog in nature, and there is a requirement to process these signals for various applications such as digital signal processing, biomedical signal processing, home automation, and also in radar applications. Therefore, we need an interface for digital-to-analog and analog-to-digital signal conversion. This can be achieved by data converters. ADC plays a very important role in converting analog signals to digital signals, which helps the systems in processing the signal in the digital domain. In this chapter, flash ADC is implemented using 20 nm TFET technology to achieve satisfactory performance with lower power dissipation. Various distinct characteristics of TFET such as ultralow leakage current, steep subthreshold slope, high ON-current-to-OFF-current ratio, delayed saturation, and unidirectional current conduction are observed in this work. Based on the distinct features, that is, unidirectional current conduction and delayed saturation in TFET, challenges in designing TFET-based circuits are identified. TFET-based sample and hold circuit, inverter, NAND gate, multiplexer, and XOR gates have been implemented. All of these functional blocks are used in the design of TFET-based comparator and thermometer-to-binary-code converter circuits. Finally, after combining these blocks, a TFET-based flash ADC has been realized that requires 15 comparators for a 4-bit flash ADC. The designed TFET-based flash ADC can work up to a 2 GS/s sampling frequency. The total power dissipation is observed to be 259 µW when operating with a power supply of 0.9 V. This work is compared with the previously reported CMOS-based flash ADC, and it is found to be more efficient in terms of power and sampling frequency. The resolution is observed to be comparable to the other references. The analysis of TFET-based flash ADC has been carried out using the HSPICE simulations with 20 nm TFET technology.
24 Jun 2022
TL;DR: In this paper , Machine Learning algorithms are used to fine-tune the Successive Stochastic Approximation Analog to Digital Converter (SSA ADC), which is used in Biomedical applications.
Abstract: Data converters implemented using CMOS technology play crucial role in electronics which is ever increasing. ADCs find their applications in signal processing and communication applications. Because of small area, low power and low/medium input signals Successive Approximation ADCs are preferred in most of the applications. Machine Learning algorithms are used to fine-tune the Successive Stochastic Approximation Analog to Digital Converter (SSA ADC), which is used in Biomedical applications. Compared to SAR ADC, SSA ADC offers low power and errors caused by DAC can be corrected to maximum possible extent using stochastic process. Various ADCs, SAR ADC and SSA ADC architectures for Biomedical applications have been compared with respect to parameters, methods and tools.
TL;DR: In this paper , a 12-bit Successive Approximation Register SAR Stochastic Analog to Digital Converter ADC topology has been designed using complementary metaloxide-semiconductor CMOS in a 0.35µm technology and a single supply voltage equal to 3.3V.
Abstract: The surrounding world is composed of continuous time and amplitude analog signals, such as the sound signal picked by a microphone, the light entering a camera, the temperature measured by a thermocouple. In order to process these real world signals by computers, they have to be converted to digital signals. Rapid advances in media technology require high performance analog to digital converters ADCs. In this work, a 12-bit Successive Approximation Register SAR Stochastic Analog to Digital Converter ADC topology has been designed using complementary metal-oxide-semiconductor CMOS in a 0.35µm technology and a single supply voltage equal to 3.3V. In order to reduce the number conversion loops in a typical SAR ADC. 8-bits of the conversion are performed using the SAR ADC and the remainder is fed to the stochastic ADC. Taking the remainder from the SAR ADC allows the input signal of the stochastic ADC to fall within a limited range. The stochastic ADC performs 4-bit conversion using 512 parallel comparators. Since a large number of comparator is used, a simple single ended comparator has been proposed. The proposed comparator reduces the dissipated power by 38% compared to the conventional single ended comparators for each comparator. The gain of the proposed comparator has doubled compared to the conventional single ended comparator. Using this hybrid conversion also solves the problem of the limited input range for stochastic ADCs. Typical stochastic ADCs have an input range around 1mV, using a SAR ADC in the first stage increased the input voltage range to 3.3 V. The ADC has a sample rate of 50Ms/s. The proposed ADC achieves an SNDR equal to 71.2 dB. The DNL -0.44/+0.47 and INL -0.55/+0.59 LSB.
TL;DR: In this article , a low-power area-efficient subarray beamforming receiver (RX) structure for a miniaturized 3-D ultrasound imaging system is presented, where the delay cells implemented with capacitors are embedded in the CDAC with significant area reduction, further eliminating the need for power-hungry ADC buffers.
Abstract: The authors present a low-power area-efficient subarray beamforming receiver (RX) structure for a miniaturized 3-D ultrasound imaging system. Given that the delay-and-sum (DAS) and digitization functions consume most of the area and power in the receiver, the beamforming successive approximation register (SAR) analog-to-digital converter (ADC) shares its capacitive digital-to-analog converter (CDAC) with the delay cells. As a result, the delay cells implemented with capacitors are embedded in the CDAC with significant area reduction, further eliminating the need for power-hungry ADC buffers. Furthermore, the dual reference 10-bit SAR ADC reduces the area of CDAC by 32 times, achieving a switching energy reduction of 98.3%, compared to the conventional SAR ADC. As a result, the proposed beamforming SAR ADC, simulated using a 0.18 μm CMOS process, consumes 230 μW per channel, significantly reducing the per channel capacitance.
TL;DR: Time-interleaved analog digital converter (TI-ADC) as discussed by the authors is an ADC that uses a fractional delay filter (Fractional Delay Filter) to improve the performance of ADC.
Abstract: Time-interleaved analog digital converter (TI-ADC)는 여러 개의 Analog digital converter (ADC) 채널을 병렬적으로 운용하여 샘플링 주파수를 높이는 기법이다. TI-ADC에서 ADC 채널 간의 샘플 시간 불일치 (Timing mismatch)는 비선형 성분을 발생시켜 Spurious free dynamic range (SFDR) 성능을 저하시킨다. TI-ADC의 샘플 시간 불일치 보정을 위해 기존의 부분 지연 필터 (Fractional delay filter)를 이용하면 오버샘플링 환경에서는 샘플 시간 불일치 보정이 가능하지만, 언더샘플링 환경에서는 샘플 시간 불일치를 제대로 보정할 수 없다. 본 논문에서는, 언더샘플링 환경에서 기존의 부분 지연 필터를 이용하면 TI-ADC의 샘플 시간 불일치가 제대로 보정되지 않는 이유를 분석하고, 언더샘플링 환경에서 샘플 시간 불일치를 보정할 수 있는 부분 지연 필터 기법을 제안한다. 이를 위해, 먼저 ADC 채널 간의 샘플 시간 불일치로 인한 위상 차이를 이용하는 샘플 시간 불일치 값 검출 알고리즘을 제안한다. 그리고 언더샘플링 환경에서 샘플 시간 불일치 보정이 가능한 부분 지연 필터의 주파수 응답을 도출한다. 제안된 부분 지연 필터의 주파수 응답은 입력 신호의 주파수에 따른 식으로 도출된다. 실험 결과에서, 제안하는 부분 지연 필터는 언더샘플링 환경에서 비선형 성분을 감소시켜 TI-ADC의 SFDR 성능을 개선시킬 수 있음을 확인할 수 있다.
25 Nov 2022
TL;DR: In this article , a comparison between stochastic flash ADC and resistor ladder flash ADC is presented in order to demonstrate how power, and area may be decreased utilizing offset voltage in design, and a Wallace tree adder and a group of comparators were employed to design the stochnastic flash analogue to digital converter (ADC).
Abstract: In this Study, a Wallace tree adder and a group of comparators were employed to design the stochastic flash analogue to digital converter (ADC). In order to demonstrate how power, and area may be decreased utilizing offset voltage in design, a comparison between stochastic flash ADC and Resistor ladder flash ADC is presented in the study. A resistor string is used to set each comparator’s trip point in a standard resistor ladder flash ADC. Random comparator offsets are compressed into digital cells by a stochastic flash ADC. A wide range of comparator offsets are compressed into digital cells by a stochastic flash ADC. A wide range of comparator offset is produced when using comparators that are implemented as digital cells. This is typically seen as a drawback, however in our situation the wide standard deviation of offset is employed to define the input signal range. The reference voltage is lower and the analog signal is always ‘‘ 1’’ if the input offset voltage of a comparator is greater than the input range of its comparator group. To produce digital output, one uses the Wallace tree adder. In a 90nm CMOS process, a stochastic flash ADC has been implemented.
28 May 2022
TL;DR: In this paper , a 2 GS/s digital-to-analog (DAC) converter is presented, which is based on a unit cell with cascoded current source and always-on switches, to enhance static linearity performance and minimize dynamic errors.
Abstract: This paper presents a 2 GS/s digital-to-analog converter designed at 1 V in 28nm, targeting an ethernet PHY IP. The 10-bit current-steering digital-to-analog converter (DAC) is a segmented implementation, comprising 6+4 bits of binary-weighted and thermometer coded sections for the LSB and MSB codes respectively. The converter is based on a unit cell with cascoded current source and always-ON switches, to enhance static linearity performance and minimize dynamic errors. The calibration approach for amplitude correction partitions the DAC unit cells in larger blocks and compensate the tail current source variation with an internal current DAC (CALDAC). The design approach demonstrates good linearity with SFDR in the region of 70 dB in low-frequency input signals, which degrades to 49.4 dB at Nyquist frequency, and the DAC shows a maximum DNL of less than 0.5. The maximum differential output swing is 0.35 $\mathrm{V}_{\mathrm{pp}}$