Showing papers on "Analog-to-digital converter published in 2023"

Low-Power Nyquist ADCs

Abstract: Analog-to-digital converters (ADCs) bridge the analog and digital worlds, which often confines the system’s performance. In portable or Internet of Things devices, the power budget is extremely tight, calling for low-power ADCs and sometimes even low supply voltage. While with a more complex modulation scheme and crowded spectrum utilization, a large dynamic range is still essential, motivating innovation in circuit, calibration, and architecture levels in the ADC designs. This chapter discusses four Nyquist ADC designs with outstanding energy efficiency. The first is a single-channel 12b 1GS/s ADC with a three-stage pipeline SAR architecture. We introduce next a SAR-TDC hybrid architecture, realizing 20 MS/s with 13b resolution. The third work is a pure pipeline ADC with a new timing arrangement, enabling a single-channel 3.3 GS/s 6b design. The last design is a time-interleaved 8b 10 GS/s TDC-based ADC. This chapter sets forth all the detailed design considerations of the four circuits.

Design of 8-Bit Hybrid Current Steering Digital to Analog Converter in a Standard 65nm CMOS Technology

Abstract: A digital-to-analog converter (DAC) in electronics is a device that transforms digital signals into analog signals. There are various DAC architectures, and DAC's usefulness for a given application is determined by factors like resolution, INL, DNL, power consumption, maximum sampling frequency, and others. Because digital-to-analog conversion may damage a signal, a DAC with negligible faults for the application should be used. The current-steered digital-to-analog converter is well suited for high-speed applications because no buffers are needed for current steering architectures and the output is the total current drawn from the supply. In this paper, an 8-bit hybrid current steering digital-to-analog converter is proposed. Four cascode current sources with different weights are used in this architecture. The UMC 65nm CMOS technology was used to design the digital-to-analog converter. The INL and DNL were +0.19/-0.15 LSB and +0.28/-0.11 LSB respectively. The DAC uses roughly 3.25 mW at a supply voltage of 1.2V and a sample rate of 100 MHz. 12.751 mV was the output voltage at full scale. In comparison to earlier reports, the power, INL, DNL, and chip area used by the digital-to-analog converter in this architecture were significantly lower. It is appropriate for use in portable devices.

Design of an integrated temperature and humidity sensor based on high dynamic range utilization rate ADC

Abstract: An integrated sensor for temperature (Temp) and humidity (RH) measurement is designed. The temperature and humidity (T/H) sensing probe are combined with one first-order discrete-time Σ-∆ analog-to-digital converter (ADC). Also, a new ample architecture of ADC is proposed, ADC selects a reasonable reference voltage according to varied range of T/H signals. Therefore, the dynamic range utilization rate of ADC is improved. The proposed sensor is designed and fabricated in 0.153μm CMOS technology. The experimental results show that the T/H sensor achieves a −0.9∼0.6% RH measurement accuracy in the humidity range of 10∼90% RH, and ±0.4℃ temperature measurement accuracy in the temperature range of −40∼120℃.

Design of Low-Power High Performance SAR Analog-To-Digital Converter Based on MOS Capacitor DAC Structure

Abstract: In this article, a 5-bit 20 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with 4.53 bits ENOB and 29.0 dB SNDR is designed using 90 nm CMOS process technology using CADENCE virtuoso. This SAR ADC consumes power of 31.67 µW with the figure-of-merit (FoM) 68.54 fJ/conv-step. A modified dynamic comparator with two inverters connected at the output to avoid metastable state of sampled signal is used, which also helps in reducing power consumption. A binary-weighted charge redistribution digital-to-analog converter (DAC) is used using metal oxide semiconductor (MOS) capacitor to lessen the power dissipation also less area requirement as compared to conventional metal–insulator-metal (MIM) capacitor-based DAC. This SAR ADC has potential application for low power and low to medium sampling rate biomedical devices.

Equivalent Number of Bits of the ADC in the Implementation of Its Input Driver Based on High-Speed Operational Amplifiers

Abstract: The article presents a mathematical analysis of a typical driver connection scheme to an analog-to-digital converter (ADC) with a differential input. The influence of circuit solutions, as well as the most significant parameters of the driver (Driver) on operational amplifiers, switched on at the input of ADC, on the equivalent bit depth of the ADC is considered. From a single point of view, an estimate is given of the reduction in the effective bit depth of the ADC, taking into account the signal delay in the parallel ADC driver. The purpose and novelty of this article is to present an analysis of the block diagram of the automatic monitoring and control system (MCS), in which the driver is located at a safe distance from the primary converter. In conclusion, the article presents the dependence of the total effective bit rate on the parameters of the ADC and the ADC driver.

Design of a 14-bit Pipelined ADC using Ring Amplifier

Abstract: With the progress of integrated circuit technology, the intrinsic gain of transistors has become increasingly low, and the power consumption and complexity of OTA operational amplifiers have become higher, increasing the overall design difficulty of pipeline ADC. In order to improve the gain of the operational amplifier, improve the overall accuracy of the ADC, and reduce circuit power consumption, a 14-bit 20MSPS analog-to-digital converter with a pipeline structure of 2.5bit-2.5bit-2.5bit-2.5bit-2.5bit-2.5bit-2.5bit-2.5bit-2bit was designed using the SMIC 40nm process and analog drive digital technology under a 1.2V power supply voltage based on a new type of ring amplifier.The simulation results show that the SNDR of the input low-frequency signal pipeline ADC is 70.47dB, the SFDR is 85.5dB, and the ENOB is 11.45bit. When inputting high-frequency signals, the SNDR of the pipeline ADC is 68.35dB, the SFDR is 81.3dB, and the ENOB is 11.07bit.

A/D Conversion with Oversample and Average Based Precision Improvement

Abstract: This paper presents high-resolution digital measurements at low cost, combining oversample and averaging. Experiments of processing data between samples and between multiple temperature sensors in the same environment are conducted. They provide results with effective increase in the analog to digital converter bits, in correspondence with the minimization on the effects of noise. It is shown that averaging a set of small, low-cost sensors at a small microcontroller can give flexible access to improved measurement accuracy.

Design and Implementation of Low Power Flash Analog to Digital Converter

Abstract: The study describes the design and modeling of 3-bit Flash type Analog to Digital converter that is power-efficient. The single inverter type comparator and multiplexer type encoder are used in the design of the FADC. The output of comparator circuit can be either “zero” or “one,” depending on the input voltage used. A single inverter comparator uses 3.799uW of electricity. The encoder using multiplexers transforms thermometer codes into equivalent digital values. The developed encoder circuit has average power consumption of 11.73nW and a latency of 2.51nseconds. Using Cadence analogue design tools in the 180nm process technology library, a 3-bit Flash ADC is created and simulated. At an operating frequency of 10MHz, the proposed design's post layout simulation results reveal average power consumption of 62.9uW and a latency of 2.832ns.

Photonic sampled and quantized analog-to- digital converters on thin-film lithium niobate platform

Abstract: In this paper, an on-chip photonic sampled and quantized analog-to-digital converter (ADC) on thin-film lithium niobate platform is experimentally demonstrated. Using two phase modulators as a sampler and a 5×5 multimode interference (MMI) coupler as a quantizer, a 1 GHz sinusoidal analog input signal was successfully converted to a digitized output with a 20 GSample/s sampling rate. To evaluate the system performance, the quantization curves together with the transfer function of the ADC were measured. The experimental effective number of bits (ENOB) was 3.17. The demonstrated device is capable of operating at a high frequency over 67 GHz, making it a promising solution for on-chip ultra-high speed analog-to-digital conversion.

A 0.5-V 10-bit Asynchronous SAR ADC with Monotonic Switching for Biomedical Applications

Abstract: In recent years, it is possible to observe a quickly adoption and daily use of wearable electronic devices such as smart watches and bracelets. Such devices have dedicated systems for monitoring biological signals, such as heartbeat and blood oxidation, and some of these devices already have the ability to provide measurements of electrocardiogram (ECG) and blood pressure signals. Additionally, these devices also feature wireless connection via Bluetooth orWi-Fi communication protocols. Both modern instrumentation and communication systems require the digitization of analog signals by means of analog-to-digital convertes (ADCs) for further digital signal processing. This work presents the design of a Successive Approximation Register (SAR) ADC for low voltage applications with 10 bits and 5 kSPS in asynchronous operating mode. The ADC is designed in 180-nm CMOS technology and operates at a nominal supply voltage of 0.5 V. Schematic-level simulations indicate that the ADC reaches a signal-to-noise-to-distortion (SNDR) ratio of 61.36 dB, leading to an effective number of bits (ENOB) of 9.90 bits. The spurious-free dynamic range (SFDR) is 73.19 dB, and the total power consumption of the ADC is 1.43 μW.

Post Silicon Characterization of Digital to Analog Converter using Arduino Uno

Abstract: This paper explains the characterization process for a DAC (Digital to Analog Converter). Parameters like DNL, INL, gain error, offset error, and their characterization processes have been discussed in detail. A remarkable change has struck the semiconductor industry where open-source Electronic Design Automation tools are being advertised to encourage people towards chip design. Tools like Open Lane support RTL to GDS flow. Companies like Google are facilitating free tape-outs of designs built using opensource PDKs like Sky Water 130 nm PDK. When the ICs are manufactured in large numbers, the fabrication process is not uniform hence, it causes variations in device behavior. Process variations may result in faulty semiconductors that can only be detected when they are tested after the tape out is done. In this paper, characterization of a DAC IC (MCP4921) has been performed without the use of an industry level characterization board and industry-level chip programmer. Arduino Uno which is an open-source micro controller has been used to program the IC by establishing an SPI interface with the DAC IC and the parameters have been measured using instruments like oscilloscope and source measure units which have been automated using Python. Python is also used to store the set of data obtained from the IC and this data is later postprocessed to calculate DC parameters like DNL, INL and Gain Error.

A 6-Bit Analog-to-Digital Converter for Electromyography Implemented Using N-Type Metal-Oxide Thin-Film Transistors

Abstract: Consisting of more than 2000 n-type metal-oxide thin-film transistors (TFTs), a 6-bit analog-to-digital converter (ADC) adopting the subranging architecture is designed, fabricated, characterized and applied to digitize an electromyogram (EMG). Consisting of amplifiers each with a feedback stage for gain-boosting, the comparators at the heart of the ADC incorporate a scheme for compensating the offset error arising from the inevitable non-uniformity of the TFT parameters. Compared to the specifications of reported ADCs based on TFTs, a higher sampling rate of 1000 S/s, a smaller differential non-linearity of 0.76 least-significant bit (LSB) and a smaller integral non-linearity of 0.88 LSB are achieved. Since the same low-temperature TFT technology for fabricating the EMG acquisition system on a flexible substrate is used to construct the ADC, the two could be readily monolithically integrated.

Low-Bit Noise-Immune Analog-to-Digital Converter

Abstract: This paper describes a new method to synthesize the structure of a low-bit analog-to-digital converter (ADC) which is based on non-linear filtering and which is noise-immune with respect to wideband noise. The proposed structure of the ADC contains so-called probabilistic relays which statistically estimate the states of the signal. The results of simulation modeling have shown effectiveness of the suggested ADC to code the input noised signal of any form providing minimal square errors comparing to the low-bit industrial ADC with and with no pre-filtering.

Dynamic Predictive Sampling Analog to Digital Converter for Sparse Signal Sensing

Abstract: This paper presents a dynamic predictive sampling (DPS) based analog-to-digital converter (ADC) that provides a non-uniform sampling of input analog continuous-time signals. The processing unit generates a dynamic prediction of the input signal using two prior-quantized samplings to compute digital values of an upper threshold and a lower threshold. The digital threshold values are converted to analog thresholds to form a tracking window. A dynamic comparator compares the input analog signal with the tracking window to determine if the prediction is successful. A counter records timestamps between the unsuccessful predictions, which are the selected sampling points for quantization. No quantization is performed for successfully predicted sampling points so that the data throughput and power can be saved. The proposed circuits were designed as a 10-bit ADC using 0.18 micro CMOS process sampling at 1 kHz. The results show that the proposed system can achieve a data compression factor of 6.17 and a power saving factor of 31% compared to a Nyquist rate SAR ADC for ECG monitoring.

Comparison of Low Power High Speed Comparator for Flash ADC

Abstract: The analog to digital converter (ADC), a bridge between digital world and analog world, plays a crucial role in the modern semiconductor industry. Among different types of ADCs, the flash ADC (also known as the direct-conversion ADC) is exceedingly fast, whose high sample rate enables many large bandwidth applications, such as optical communication, radar detection. The comparator circuit is one of the critical components of flash ADC. The characteristics, like latency, gain and power consumption, of comparators determine the overall performance of flash ADCs. This paper analyzes and compares different types of comparator architecture and suggests a high-performance design for flash ADC.

Estimation of Parameters of Photonic Analog-to-Digital Converters

Abstract: The defining element of digital radio receivers is an analog-to-digital converter. ADCs implemented using microwave photonics are reaching a new level in performance. The properties and characteristics of converters of practical interest when used in the structure of radio receivers are considered. The advantage of the sampling frequency achieved by the ADC is determined, which allows processing GHz band signals without using frequency shift and pre-filtering. The possibility of increasing the carrier-to-noise ratio and the effective number of bits by increasing the average power on the photodiode is determined. A variant of increasing the average power on the diode by amplifying the modulating signal is presented. The requirements for the structure of the analog part to meet the conditions for increasing CNR and for using the full scale of the converter are determined.

Equivalent Number of Bits of Major ADC Types Considering the Evaluation of Their Dynamic Error

Abstract: Data on the equivalent (real) number of bits of an analog-to-digital converter (ADC), taking into account its operating conditions, makes it possible to make the optimal choice of ADC at the early stages of designing analog-to-digital control systems. The article shows that the real number of bits is determined by the signal delay times in the ADC and the time sampling frequency of the signals converted into the ADC, which depends on the cutoff frequency of the characteristic of the spectral density of the converted signal. The analysis carried out during the research made it possible to obtain specific dependences of the delay times of the converted signals in the ADCs under consideration. The article gives a comparative assessment of the influence of the time characteristics of three types of sequential ADCs (sequential count, push-pull integration, successive approximation) on the equivalent number of bits of the analog-to-digital conversion process.

Designing and simulation a 15-bit successive approximation register analog-to-digital converter

Abstract: Analog-to-digital converters (ADC) are widely employed to monitor long-term signal characteristics in wireless sensor networks and healthcare electronic devices. It is critical in these applications to use an energy-efficient ADC to extend battery life. This paper presents a 15-bit successive-approximation register (SAR) ADC for using in biomedical processing systems. The segmentation degrees (the amount of bits in each divided capacitive sub-array) are optimized to minimize switching power and area based on linearity and matching requirements. The proposed SAR ADC is simulated by using Simulink of Matlab. The simulated results show that the ADC achieves 14.78-bit of effective numbers of bits (ENoB), 111.5 dB of the spurious-free dynamic range (SFDR) with 90.74 dB of signal-to-noise ratio (SNR) at a sampling rate of 10MHz.

Analog-digital converter of wideband signals with correction of linearity errors

Abstract: The widespread use of analog-to-digital converters (ADC) in computer systems is hindered by low resolution when converting signals in a wide frequency band. These problems are related both to the lack of the necessary elementary base and to the complexity of the processes of analog-digital conversion of broadband signals random in time, the mathematical representation of which in the time and frequency dimensions is quite complex. This results in high linearity errors of the ADC, which reduce the efficiency of the analog-to-digital conversion of broadband signals in computer systems. It is proposed to solve the problem of increasing the resolution of broadband analog-to-digital conversion devices by increasing the linearity of the ADC. A modified method of increasing the linearity of the ADC by adjusting it in the dynamic mode is presented. Such adjustment is performed by using a statistical methodology for evaluating the characteristics of broadband signals. The use of a test effect in the form of a multi-tone signal during calibration of the ADC is justified. The proposed test signal has a frequency spectrum enriched with fundamental harmonics and can be implemented using a wide class of standard sinusoidal signal generators with normalized metrological characteristics. At the same time, such a test signal makes it possible to ensure the operation modes of the ADC that are adequate to the real conditions of operation of analog-to-code converters. In order to maintain the high speed of the ADC, it is proposed to perform the adjustment by replacing the source code of the ADC with the corrected code. A structural diagram of the device for analog-to-digital conversion of broadband signals with correction of linearity errors has been developed, in which digital-to-analog formation of the test signal and tabular formation of corrected codes are used. An analysis of the dynamic parameters of the ADC with linearity error correction was performed, which confirmed the high efficiency of the proposed method of statistical evaluation and error correction and the high resolution of the constructed ADC structure.

Building an ultra low-power analog-to-digital converter for medical applications

Abstract: Medical implant devices require as little power consumption as possible, and a collection of new techniques enables even lower limits.

Successive Approximation Register Analog-to-Digital Converter—A Tutorial

Abstract: This tutorial paper covers two crucial aspects of successive approximation register (SAR) analog-to-digital converter (ADC). First, a mathematical analysis for two commonly used SAR ADC topologies is presented, and then the power dissipation aspect of SAR ADC is discussed for different switching schemes. The paper also provides some design criteria for practical implementation of SAR ADCs.

Analysis of the influence of final resolution on ADC accuracy

Abstract: This work is devoted to the study of the influence of quantization noise on the spectral characteristics of a digital signal and the assessment of spectrum measurement errors that arise due to the quantization noise of an analog-to-digital converter. To achieve more accurate and reliable measurements of the spectrum, an error assessment was carried out, which allows taking into account the impact of quantization noise on the spectral data. This is important for obtaining more accurate results and ensuring high-quality measurements of the spectral components of the vibration signal. In addition, further research is aimed at developing methods for estimating spectrum measurement errors taking into account other possible sources of errors and contributing to the development of compensation algorithms to reduce the impact of quantization noise.

An Analog Side-channel Attack on a High-speed Asynchronous SAR ADC using Dual Neural Network Technique

Abstract: This brief presents a side-channel attack (SCA) technique on a high-speed asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed dual neural network based on multiple noise waveforms separately discloses sign and absolute value information of input signals which are hidden by the differential structure and high-speed asynchronous operation. The target SAR ADC and on-chip noise monitors are designed on a single prototype chip for SCA demonstration. Fabricated in 40 nm, the experimental results show the proposed attack on the asynchronous SAR ADC successfully restores the input data with a competitive accuracy within 300mV rms error.

High-speed all-optical digital-to-analog converter based on photonic crystal ring resonators

Abstract: Abstract In this paper, a 2-bit all-optical digital-to-analog converter, including two ring resonators has been presented. Some nonlinear rods have been placed at the center of the rings which their refractive indices depend on the incoming optical intensity. Concerning the states of two input bits, each ring does the switching operation and guides the optical waves toward the output port. The finite difference time domain method has been used to calculate the electric and magnetic components of optical waves. The maximum absolute error of the digital-to-analog converter is equal to 2.43 %, less than the previous works. Also, the insertion loss varies from −11.13 dB to −8.57 dB for the different states. Besides, the maximum propagation time of the structure is just 1.8 ps suitable for high-speed applications.

180 nm FLASH ANALOG TO DIGITAL CONVERTOR

Abstract: In this paper, Threshold Inverter Quantizer (TIQ) is a novel idea which can effectively replace the reference voltage generator, resistive/capacitive voltage divider network and array of differential comparators in a conventional flash Analog to Digital Converter (ADC) by an internal reference comparator array constructed of Complementary Metal Oxide Semiconductor (CMOS) inverters. The inverter threshold voltage serving as the reference voltage, this architecture claims large improvements in terms of silicon area, power consumption and operating speed. Perturbations due to sensitivity of the inverter threshold voltage to operating temperature/process variations pose impediments in such ADC designs and strongly demand a compensation scheme to such variations. This paper presents a TIQ based flash ADC, with inverter threshold voltage compensation. In this project 5 bit flash adc using TIQ Comparator is designed and simulated using TANNER EDA in 180nm technology. Key Words: flash, adc, tiq(threshold inverter quantization)