Showing papers on "Arithmetic logic unit published in 1987"

Graphics display system having data transform circuit

Abstract: A graphics display system (10) includes a display screen (14) on which images are formed and a data transform circuit (12) that provides transformations between model data representing the basic shape of an object and display data that are employed in the formation of an image of the object on the display screen. The model data are transformed into display data in accordance with position data and orientation data that correspond, respectively, to a translation and a rotation of the image on the display screen. The data transform circuit communicates with a central processing unit (30) that controls the operation of the graphics display system. The data transform circuit includes data storage registers (34, 36, 38, 40, 42, 44, 46) that receive and hold the model, position, and orientation data. A multiplier circuit (68) and an adder circuit (112) calculate the transformation of the model data into display data. A data transform controller circuit (50) controls the transfer of data from the data storage registers to the multiplier and adder circuits so that the transformation takes place at a relatively high speed. The data transform circuit of this invention allows the transformation to proceed without delays such as those caused by the repetitive transfer of output data back to the inputs of an arithmetic logic unit.

High-speed binary and decimal arithmetic logic unit

Abstract: A combined binary and binary coded decimal (BCD) arithmetic logic unit (ALU) having a binary ALU adapted to perform decimal operations on BCD data without impacting the performance of binary operations. Said combined binary and BCD ALU comprises a look-ahead carry binary ALU for generating the binary sum or logical combination of inputs to the binary ALU to an output (Y), arranged in groups of four bits, and providing carry outputs (Co) of the binary additions from each of the groups of four bits of the Y output; a decimal correction means, responsive to the Y and Ci outputs from the binary ALU means, for correcting the binary sum from the binary ALU means when performing BCD arithmetic, and; a multiplexer for selecting output from the binary ALU means or from the binary ALU means to a result output, wherein the output from the binary ALU means is selected for performing operations on binary data and output from the decimal correction means is selected for performing operations on BCD data.

Digital signal processor architecture with an ALU and a serial processing section operating in parallel

Abstract: A digital signal processor (DSP) for conducting arithmetically complex functions, is provided. The DSP is preferably embodied as a single integrated circuit chip and generally includes a microinstruction sequencer (MIS) section, an arithmetic logic unit (ALU), a serial arithmetic processor section, a RAM section, and a system data bus. The MIS includes a coded ROM, a circuit for addressing the ROM, a ROM decoder for decoding the ROM code into control and data signals, and circuitry for sending the control and data signals to desired locations, and controls the functioning of the DSP. The ALU performs arithmetic and logic functions under the control of the ROM, while the serial arithmetic processor section conducts arithmetically complex functions under the control of the ROM. The RAM, under control of the ROM receives and stores data which is sent to the RAM via a system data bus directly from the ROM, from the ALU, from the serial arithmetic processor, and from circuitry exterior to the DSP. The RAM also sends via the data bus data to the ALU, the serial arithmetic processor, the microinstruction sequencer and the circuitry exterior to said digital signal processor under control of the ROM. The provided DSP is particularly advantageous in carrying out ADPCM algorithms.

Galois field arithmetic logic unit

Abstract: The present invention relates to a Galois field arithmetic logic unit of a code error check/correct apparatus to be employed when recording/reproducing data on an optical disk. The arithmetic logic unit uses a combination including a parallel multiplication circuitry of a primitive element α of a Galois field, an EX-OR addition circuitry for the multiplication resuts, a 0 element decision circuitry for the results of the addition, the registers to which the multiplication results are fed back so as to accomplish a parallel computation of a polynomial, thereby enabling a root and an error value of an error location equation to be obtained at a high speed. The arithmetic logic unit develops a remarkable reduction of the amount of computation particularly when the code system has a great code length and the degree of the error location polynomial associated with the long distance code is as high as d=17.

Apparatus for reading to and writing from memory streams of data while concurrently executing a plurality of data processing operations

Abstract: A pair of arithmetic logic units for receiving instruction to perform data transformations are positioned in tandem relation between an input bus and an output bus which are both connected to a register file. Data paths connect the register file to the input and output buses for transferring data from the register file to the arithmetic logic units. One arithmetic logic unit has a pair of input ports connected to the input bus and an output port connected to the input of the second arithmetic logic unit. The second arithmetic logic unit has a second input port connected to the input bus and an output port connected to the output bus. The tandem arrangement of arithmetic logic units are pipelined to operate concurrently to provide twice the data transformation capability of a single arithmetic logic unit in a data processor. With this arrangement streams of data are concurrently transformed by the tandem arrangement of arithmetic logic units to perform vector operations. With this arrangement control flow calculations are concurrently executed separately thus allowing the arithmetic logic units to compute data transformations at every moment. As a result procedure call parameters do not consume the general-purpose register since they are stored in a data value queue not saved or stored across procedure boundaries.

Color graphic processor for performing logical operations

Abstract: A color graphic processor includes one or more processing elements responsive to pixel data provided by a frame buffer. The processing element stores pixels from the frame buffer in source and destination registers. The arithmetic logic unit (ALU) portion of the processing element includes a random access memory (RAM) addressed by the registers to produce a result pixel value which can be written back to the frame buffer. The RAM can implement a wide variety of pixel operations by loading the RAM with operation specific data.

A microprogrammable real-time video signal processor (VSP) LSI

Abstract: A microprogrammable real-time video signal processor (VSP) LSI has been developed for constructing a parallel video signal processing system. The VSP LSI employs a flexible multistage pipelined architecture and can handle such sophisticated image signal processing as high-speed edge detection and motion compensation. It contains many operational function units such as an arithmetic logic unit and with absolute value calculation capability, a minimum/maximum value detector, a two-port SRAM, RAM address pointer and clocked bus lines. The VSP LSI has been designed using two different kinds of automatic layout programs. The chip, which was fabricated with a 2.5-/spl mu/m CMOS and double-layer metallization technology, has an area of 9.91/spl times/9.50 mm/SUP 2/ and contains about 48000 MOSFETs. It operates at a clock frequency of 14.3 MHz with a single 5-V power supply and typically consumes 240 mW. An experimental system, using a single VSP LSI chip, has been constructed in order to demonstrate various application capabilities, such as interframe difference operations, high-speed edge detection and motion compensation.

Arithmetic and logic unit with prior state dependent logic operations

Abstract: The present invention is an arithmetic and logic unit of a microprocessor having hardware improved to execute specified operation such as operation of MAD (modified addition) by a small number of instruction steps. The arithmetic and logic unit of the present invention has a control portion provided with a control circuit for performing the specified operation such as operation of MAD by a small number of instruction steps.

Microcode computer having dispatch and main control stores for storing the first and the remaining microinstructions of machine instructions

Abstract: A computer includes a memory for storing the machine instructions therein and an arithmetic logic unit for carrying out logical and arithmetic operations. An instruction processing unit is provided for receiving and decoding machine instructions which are received from the memory. The instruction processing unit produces an entry address for the first microinstruction which corresponds to the machine instruction which was decoded by the instruction processing unit. A dispatch control store is connected to receive the entry address and further has stored therein the first microinstruction for each of the machine instructions. The dispatch control store produces a selected one of the microinstructions stored therein upon receipt of the entry address. A main control store is provided for storing therein all of the microinstructions for each of the machine instructions other than the first microinstruction for each of the machine instructions. Circuitry is provided for conveying the entry microinstruction corresponding to the entry address from the dispatch control store to the arithmetic logic unit and subsequently for conveying sequentially the remainder of the microinstructions from the control store to the arithmetic logic unit for decoded machine instruction.

Apparatus and method for an extended arithmetic logic unit for expediting selected floating point operations

Abstract: Apparatus and method for expediting the alignment of the fraction portion of operands in floating point operations. The alignment is performed in the arthmetic logic unit where the argument of the operand A exponent is subtracted from the argument of the operand B exponent. Because the result B-A can be a negative quantity, the result A-B can also be required. The arthmetic logic unit of the present invention provides additional apparatus for simultaneously determining B-A and A-B. The additional apparatus includes components in the propagate bit and generate bit cell for determining an auxiliary generate bit; an additional carry-chain array for combining the carry-in signal, the propagate bit and the auxiliary generate bit; and selection circuits for selecting the appropriate result.

Parallel arithmetic-logic unit for as an element of digital signal processor

Abstract: A parallel arithmetic-logic unit (PALU) controlled by a microinstruction sequencer and capable of executing conditional operations in a single pass is disclosed. The PALU generally comprises first and second registers for storing data, a comparator for continually comparing the values in the registers, and an arithmetic-logic core connected to the registers for performing arithmetic, logical and data move operations on the data in the registers. The comparator is preferably an unsigned magnitude comparator which outputs flags indicative of the relative status of the values in the registers. The flags are read by a microinstruction sequencer which then uses the flag information to determine what operation the arithmetic-logic core is to conduct. Preferably, a shifter is also provided between one of the registers and the arithmetic-logic core.

Toward an ideal computer arithmetic

Abstract: A new computer arithmetic is described. Closely related built-in functions are included. A user's point of view is taken, so that the emphasis is on what language features are available to a user. The main new feature is flexible precision control of decimal floating-point arithmetic. It is intended that the language facilities be sufficient for describing numerical processes one might want to implement, while at the same time being simple to use, and implementable in a reasonably efficient manner. Illustrative examples are based on experience with an existing software implementation.

A general purpose arithmetic logic unit

Abstract: A fast arithmetic and logic unit (ALU) has been constructed as a single CAMAC unit. This device has been designed to provide both arithmetic and logical operations on two 16-bit data fields. The ALU will be put into practical use in the energy trigger of the L3 experiment at LEP, CERN. Due to its simplicity and flexibility the circuit may have applications in other high energy physics experiments. In this paper we describe the details of this circuit.

Polynomial vector arithmetic operation control system

Abstract: A system for controlling polynomial arithmetic operations of a vector arithmetic processor capable of executing the arithmetic operations independently of a central processing unit (CPU), includes, in the vector arithmetic processor, a circuit for modifying an instruction code supplied from the CPU on the basis of a signal representing that the instruction supplied from the CPU is a vector arithmetic instruction and a signal for commanding switching of the instruction code from the CPU, and an instruction decoder addressed in response to an output from the modification circuit to output an instruction word to an arithmetic unit.

Digital signal processor with divide function

Abstract: A digital signal processor which efficiently executes the division of a positive number in N+1 processor cycles where N is equal to the number of digits in the dividend. This is achieved by utilizing an arithmetic logic unit in the processor which is divided into two selectively concatenated independently controllable sections so that the values therein can be selectively processed under control of a unique algorithm.

A systematic technique for detecting and locating bridging and stuck-at faults in I/O pins of LSI/VLSI chips

Abstract: In VLSI chips the detail circuit implementation is unknown in nearly all cases; only the behavior is known to the user. In this paper, we present a systematic way to detect and to locate both stuck-at and bridging faults in input/output pins of integrated circuit chips and printed circuit boards by using a sequence of special test patterns which produce distinct output responses. This allows us to test all stuck-at and bridging faults in I/O (input/output) pins independent of the circuit implementation. Some examples are given to show how to detect and locate all possible stuck-at and bridging faults in I/O pins of RAM (random access memory), and ALU (arithmetic logic unit). The generated test patterns are verified by a digital computer to ensure the completeness of test set. A systematic scheme for generating tests for locating bridging and stuck-type faults at I/O pins of IC chips is presented. Results of computer implementation and execution of the scheme are reported.

Circuitry for character translate functions

Abstract: In a data processing system that includes a central processing unit (CPU) which performs functions on data characters based upon a set of program instructions, the central processing unit being of a type that includes: (a) an arithmetic logic unit for performing the functions on the data characters; (b) a plurality of internal registers for storing data characters; (c) a data bus both for transferring data characters internally within the CPU and for transmitting data characters to and receiving data characters from devices external to the CPU; and (d) an address bus for transmitting receiving addresses of referenced program instructions, and wherein the contents of one of the internal registers forms part of the address of the referenced program instruction available on the address bus. The improvement comprising a storage unit which includes a plurality of data character storage locations which are addressed by the contents of the internal register available on the address bus such that the storage location is written if the referenced instruction is an output and read if the referenced instruction is an input.

A Josephson 2-bit arithmetic logic unit

Abstract: A Josephson 2-bit arithmetic logic unit (ALU) is presented. A four-junction logic (4JL) gate-family is used in the ALU circuit. The ALU circuit is designed based on a dual-rail logic to perform both the arithmetic and the logic functions. The circuit was fabricated with Nb/Al-oxide/Nb tunnel junctions using a 3- {\mu}m minimum line width technology. For each 16 functions, the circuit was completely confirmed in consistent logic operations. The operating time was measured to be 165 ps in the arithmetic function of subtraction, A minus B . Power dissipation was estimated to be 581 {\mu}W in the circuit.

Fault-Tolerant VLSI Processor

Abstract: The paper describes the architecture of a fault tolerant processor Within the functional core consisting of ALU (Arithmetic Logic Unit), CCU (Computer Control Unit), PCU (Program Control Unit) and I/O-Unit all single errors can be corrected The basic principle is the application of arithmetic, biresidual coding and linear parity coding to protect the states of the processor as well as the use of opcode-signature analysis, address changing counter and current/future check symbol technique to check the changes in the states of the processor The architecture supports the flexible employment of fault tolerance There are four software- controlled check-levels: check of all micro operations, check of the macro operations, check of the program flow and no check at all The redundancy caused by coding and code-checking can be utilized for a self-test of the processor This self-test based on coded, on-chip generated test patterns runs at the normal data rate of the processor without the need of an external reference

Sequentially performing arithmetic operations on data sets.

Abstract: Data sets (X, Y, Z) along with associated instructions from an instructions register (IR) are sequenced through an arithmetic processing unit (APU) for performing a plurality of arithmetic operations on each of the data sets in accordance with an associated instruction. The arithmetic processing unit has a plurality of interconnected computational pipelines each including a plurality of groups (80X, 80Y, 80Z, 82X, 82Y, 82Z, etc.) of arithmetic elements arranged to perform a sequence of arithmetic operations on the data set in accordance with the associated instruction. The data sets and the associated instructions are applied to the processing unit for propagation therethrough such that the instruction propagates through pipelined instruction registers (84R, 86R) in sequence with the data set propagating through the pipelined arithmetic elements.

Arithmetic and logic operating unit

Abstract: An arithmetic and logic unit control circuit includes arithmetic circuits (10a-10d) for generating the absolute value |A| of an input signal A and the complement B of an input signal B from n-bit input signals A and B in response to a control signal from a controller (14). Full adders (6a-6d) add outputs from the arithmetic circuits in response to a control signal from the controller (14). First logic circuits (20a-20c, 21) extract the most significant bit of (|A|-B) to form outputs of the full adders (6a-6d) in response to a control signal from controller (14) and second logic circuits (20e, 21) to perform a three-level decision of values A and B from the outputs of the first logic circuits (20a-20c, 21) and the most significant bit of the input signal A. The arithmetic and logic unit can thereby perform Alternate Mark Inversion (AMI) coding in one machine cycle.

A Novel Approach to Block Floating Point Arithmetic for Digital Signal Processor Design

Abstract: Block floating-point arithmetic is considered as an alternative to fixed-point and floating-point arithmetic in the implementation of recursive digital signal processing algorithms. Block floating-point implementation of state-space digital structures is shown to have improved signal-to-noise ratio compared to fixed-point implementation and can be designed to be free of overflow. The maximum amplitude of zero input limit cycle is limited to 1 bit. Architecture suitable for the VLSI implementation of a block floating point co-processor is described.

Processing system for transfer instruction of information processor

Abstract: PURPOSE:To produce the transfer data with high efficiency by providing a shifter control part which can decide the number of shifts based on the difference between both data areas and a mechanism which can regard the partial data width as four bytes. CONSTITUTION:A shifter control part 1-10 gives the arithmetic output of an arithmetic logic unit 1-4 to a shift arithmetic unit 1-3 as the shift number, a store data register 1-12 can decide whether only the upper half, the lower half or both upper and lower halves are set when the data is set from a certain register and a shifter input part 1-9 can combine the upper data at one side and the lower data at the other side and supply them to the unit 1-3 are provided to the titled system. Thus the executing time of a transfer instruction can be shortened without increasing the hardware quantity so much in case the transfer transmitter data area address and the transfer receiver data area address overlap with each other by a difference of eight bytes or less.

Thirty-two-bit bit slice.

Abstract: A thirty-two bit, cascadable, microprogrammable, bit-slice is disclosed which includes a seven-port random access memory (RAM) unit, a funnel shifter, a mask generator, an arithmetic logic unit (ALU), and a merge logic unit.

Full adder circuit

Abstract: An inverting full adder circuit is provided for use in a ripple-carry adder or arithmetic logic unit (ALU) which includes a plurality of similar full adder stages connected in series such that the carry delay from one stage to the next is minimized, and which requires fewer devices and less space on the surface of a semiconductor chip than do known adders or ALUs of comparable performance This invention may use either N-channel field effect transistors, ie, NMOS technology, or it may use complementary metal oxide semiconductor (CMOS) technology

Variable display device for level of acoustic equipment

Abstract: PURPOSE:To display a setting level before application of power without any backup power supply and to eliminate the error between an actual setting level and the display by providing a level detector and an A/D converter to a conventional display CONSTITUTION:When a key input device 6 sets a level to an arithmetic logic unit 7, the unit 7 activates a level variable device 8 to a set level and a level detector 9 detects the output A detected analog quantity is converted into a digital quantity by an A/D converter 10 and the unit 7 transfers the display data to the display device 11 based on the digital quantity Thus, the level set actually and the displayed level are made coincident Further, the similar performance is attained without any backup power supply

Computer containing pre-shifter

Abstract: PURPOSE:To perform the multiplication using a shift-addition instruction at a high speed by using a pre-shifter which shifts the data stored in a register by a designated amount with an instruction and supplies the data to an arithmetic logic unit ALU. CONSTITUTION:A computer contains a pre-shifter 103 connected to one of the inputs of an ALU102. An instruction 110 which executes as index-qualified load instruction or a store instruction shown whether or not an index register 1011 (general-purpose register) should perform the multiplication with the number of bytes contained in each unit of data undergone an access. This multiplication is executed by shifting the contents of the register 1011 by the pre-shifter 103 before the ALU102 performs an address calculation. In this case, the shift, addition, subtraction and shift-addition instructions are used respectively.