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Showing papers on "Atomic layer deposition published in 2001"


Patent
02 Mar 2001
TL;DR: In this paper, a graded gate dielectric (72) is provided, even for extremely thin layers, which can be varied from pure silicon oxide to oxynitride to silicon nitride.
Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles (301) or (450, 455, 460, 470) including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources (306 or 460) are introduced during the cyclical process. A graded gate dielectric (72) is thereby provided, even for extremely thin layers. The gate dielectric (72) as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric (72) can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (432) (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses (460) can gradually increase in frequency, forming a graded transition region (434), until pure copper (436) is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

520 citations


Patent
19 Nov 2001
TL;DR: In this article, the surface termination of the substrate with a low temperature radical treatment is used to facilitate subsequent deposition without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.
Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material. Preferably less than 10 Å of the bulk material incorporates the excited species, which can include fluorine, chlorine and particularly nitrogen excited species.

483 citations


Patent
31 May 2001
TL;DR: In this article, a first layer comprising a first element that is chemisorbed to a surface of a substrate, by exposing the surface to a first source gas having molecules therein that comprise the first element and a halogen.
Abstract: Methods of forming thin films include forming a first layer comprising a first element that is chemisorbed to a surface of a substrate, by exposing the surface to a first source gas having molecules therein that comprise the first element and a halogen. A step is then performed to expose the first layer to an activated hydrogen gas so that halogens associated with the first layer become bound to hydrogen provided by the activated hydrogen gas. The first layer may then be converted to a thin film comprising the first element and a second element, by exposing a surface of the first layer to a second source gas having molecules therein that comprise the second element.

447 citations


PatentDOI
TL;DR: In this paper, an OLED display device including an encapsulation assembly and methods for making such devices is described. But the present invention is not directed to an actual OLED display, it is directed to the assembly of a dielectric oxide layer in contact with at least part of a substrate.
Abstract: The present invention is directed to an OLED display device including an encapsulation assembly and methods for making such devices. The encapsulation assembly includes at least two layers, one of which is a dielectric oxide layer directly in contact with at least part of a substrate, and the other of which is preferably a polymer layer.

403 citations


Patent
20 Jun 2001
TL;DR: An atomic layer deposition method of forming a solid thin film layer containing silicon is described in this article, where a substrate is loaded into a chamber and a first portion of a first reactant is chemisorbed onto the substrate, and a second portion of the first reaction on the substrate is purged from the substrate and the chamber.
Abstract: An atomic layer deposition method of forming a solid thin film layer containing silicon. A substrate is loaded into a chamber. A first portion of a first reactant is chemisorbed onto the substrate, and a second portion of the first reactant is physisorbed onto the substrate. The physisorbed portion is purged from the substrate and the chamber. A second reactant is injected into the chamber. A first portion is chemically reacted with the chemisorbed first reactant to form a silicon-containing solid on the substrate. The first reactant is preferably Si[N(CH 3 ) 2 ] 4 , SiH[N(CH 3 ) 2 ] 3 , SiH 2 [N(CH 3 ) 2 ] 2 or SiH 3 [N(CH 3 ) 2 ]. The second reactant is preferably activated NH 3 .

353 citations


Patent
23 Jul 2001
TL;DR: In this article, a method of forming a metal layer having excellent thermal and oxidation resistant characteristics using atomic layer deposition is provided, which can be employed as a barrier metal layer, a lower electrode or an upper electrode in a semiconductor device.
Abstract: A method of forming a metal layer having excellent thermal and oxidation resistant characteristics using atomic layer deposition is provided. The metal layer includes a reactive metal (A), an element (B) for the amorphous combination between the reactive metal (A) and nitrogen (N), and nitrogen (N). The reactive metal (A) may be titanium (Ti), tantalum (Ta), tungsten (W), zirconium (Zr), hafnium (Hf), molybdenum (Mo) or niobium (Nb). The amorphous combination element (B) may be aluminum (Al), silicon (Si) or boron (B). The metal layer is formed by alternately injecting pulsed source gases for the elements (A, B and N) into a chamber according to atomic layer deposition to thereby alternately stack atomic layers. Accordingly, the composition ratio of a nitrogen compound (A—B—N) of the metal layer can be desirably adjusted just by appropriately determining the number of injection pulses of each source gas. According to the composition ratio, a desirable electrical conductivity and resistance of the metal layer can be accurately is obtained. The atomic layers are individually deposited, thereby realizing excellent step coverage even in a complex and compact region. A metal layer formed by atomic layer deposition can be employed as a barrier metal layer, a lower electrode or an upper electrode in a semiconductor device.

350 citations


Patent
24 Oct 2001
TL;DR: The atomic layer deposition (ALD) process is based upon the sequential supply of at least two separate reactants into a process chamber as discussed by the authors, where a first reactant reacts (becomes adsorbed) with the surface of the substrate via chemisorption.
Abstract: An atomic layer deposition (ALD) process is based upon the sequential supply of at least two separate reactants into a process chamber. A first reactant reacts (becomes adsorbed) with the surface of the substrate via chemisorption. The first reactant gas is removed from the chamber, and a second reactant gas reacts with the adsorbed reactant to form a monolayer of the desired film. The process is repeated to form a layer of any thickness. To reduce the process time, there is no separate purge gas used to purge the first reactant gas from the chamber prior to introducing the second gas, containing the second reactant. Instead, the purge gas also includes the second reactant. Thus, there can be very little or no delay between introducing the first and second gases. In one embodiment, a plasma of the second gas is created using an RF source, which forms energized ions and reactive atoms to drive the reaction at low temperatures.

339 citations


Patent
28 Jun 2001
TL;DR: The use of these nitrate-based precursors is well suited to forming high dielectric constant materials on hydrogen passivated silicon surfaces, such as nanolaminates of hafnium oxide and zirconium oxide.
Abstract: Methods of forming hafnium oxide, zirconium oxide and nanolaminates of hafnium oxide and zirconium oxide are provided. These methods utilize atomic layer deposition techniques incorporating nitrate-based precursors, such as hafnium nitrate and zirconium nitrate. The use of these nitrate based precursors is well suited to forming high dielectric constant materials on hydrogen passivated silicon surfaces.

327 citations


Patent
26 Apr 2001
TL;DR: In this paper, the conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials, is described, and a method and structures for conformal linings are provided.
Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.

307 citations


Patent
25 Sep 2001
TL;DR: In this paper, a method for forming a tungsten-containing copper interconnect barrier layer on a substrate with a high (e.g., greater than 30%) sidewall step coverage and ample adhesion to underlying dielectric layers is presented.
Abstract: A method for forming a tungsten-containing copper interconnect barrier layer (e.g., a tungsten [W] or tungsten-nitride [WxN] copper interconnect barrier layer) on a substrate with a high (e.g., greater than 30%) sidewall step coverage and ample adhesion to underlying dielectric layers. The method includes first depositing a thin titanium-nitride (TiN) or tantalum nitride (TaN) nucleation layer (12) on the substrate, followed by the formation of a tungsten-containing copper interconnect barrier layer (20) (e.g., a W orWxN copper interconnect barrier layer) overlying the substrate. The tungsten-containing copper interconnect barrier layer can, for example, be formed using a Chemical Vapor Deposition (CVD) technique that employs a fluorine-free tungsten-containing gas (e.g., tungsten hexacarbonyl [W(CO)6]) or a WF6-based Atomic Layer Deposition (ALD) technique. The presence of a thin TiN (or TaN) nucleation layer facilitates the formation of a tungsten-­containing copper interconnect barrier layer with a sidewall step coverage of greater than 30% and ample adhesion to dielectric layers. A copper interconnect barrier layer structure includes a thin titanium-nitride (TiN) (or tantalum nitride [TAN]) nucleation layer disposed directly on the dielectric substrate (e.g., a single or dual-damascene copper interconnect dielectric substrate). The copper interconnect barrier layer structure also includes a tungsten-­containing copper interconnect barrier layer (e.g., a W or WxN copper interconnect barrier layer) formed on the thin TiN (or TaN) nucleation layer using, for example, a CVD technique that employs a fluorine-free tungsten-containing gas (e.g., [W(CO)6]) or a WF6-based ALD technique.

307 citations


Patent
23 May 2001
TL;DR: An atomic layer deposition (ALD) process deposits thin films for microelectronic structures, such as advanced gap and tunnel junction applications, by plasma annealing at varying film thicknesses to obtain desired intrinsic film stress and breakdown film strength as mentioned in this paper.
Abstract: An atomic layer deposition (ALD) process deposits thin films for microelectronic structures, such as advanced gap and tunnel junction applications, by plasma annealing at varying film thicknesses to obtain desired intrinsic film stress and breakdown film strength. The primary advantage of the ALD process is the near 100% step coverage with properties that are uniform along sidewalls. The process provides smooth (R a ˜2 Å), pure (impurities<1 at. %), AlO x films with improved breakdown strength (9–10 MV/cm) with a commercially feasible throughput.

Patent
11 Sep 2001
TL;DR: In this paper, a high-k dielectric material is sandwiched between two layers of aluminum oxide or lanthanide oxide in the formation of a transistor gate or memory cell.
Abstract: An ultrathin aluminum oxide and lanthanide layers, particularly formed by an atomic layer deposition (ALD) type process, serve as interface layers between two or more materials. The interface layers can prevent oxidation of a substrate and can prevent diffusion of molecules between the materials. In the illustrated embodiments, a high-k dielectric material is sandwiched between two layers of aluminum oxide or lanthanide oxide in the formation of a transistor gate dielectric or a memory cell dielectric. Aluminum oxides can serve as a nucleation layer with less than a full monolayer of aluminum oxide. One monolayer or greater can also serve as a diffusion barrier, protecting the substrate from oxidation and the high-k dielectric from impurity diffusion. Nanolaminates can be formed with multiple alternating interface layers and high-k layers, where intermediate interface layers can break up the crystal structure of the high-k materials and lower leakage levels.

Patent
10 May 2001
TL;DR: In this article, a system and method for that allows one part of an atomic layer deposition (ALD) process sequence to occur at a first temperature while allowing another part of the ALD process sequence at a second temperature.
Abstract: A system and method for that allows one part of an atomic layer deposition (ALD) process sequence to occur at a first temperature while allowing another part of the ALD process sequence to occur at a second temperature. In such a fashion, the first temperature can be chosen to be lower such that decomposition or desorption of the adsorbed first reactant does not occur, and the second temperature can be chosen to be higher such that comparably greater deposition rate and film purity can be achieved. Additionally, the invention relates to improved temperature control in ALD to switch between these two thermal states in rapid succession. It is emphasized that this abstract is provided to comply with rules requiring an abstract. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. [37 C.F.R. §1.72(b)].

Patent
06 Mar 2001
TL;DR: In this paper, a graded gate dielectric is provided, even for extremely thin layers, whereby the composition of the film can be varied from monolayer to monollayer during cycles including alternating pulses of self-limiting chemistries.
Abstract: Thin films are formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO 2 ) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a graded transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

Patent
19 Jan 2001
TL;DR: In this article, a method of forming a metal nitride film using chemical vapor deposition (CVD), and a method for forming metal contact and a semiconductor capacitor of a semiconducted device using the same, are provided.
Abstract: A method of forming a metal nitride film using chemical vapor deposition (CVD), and a method of forming a metal contact and a semiconductor capacitor of a semiconductor device using the same, are provided. The method of forming a metal nitride film using chemical vapor deposition (CVD) in which a metal source and a nitrogen source are used as a precursor, includes the steps of inserting a semiconductor substrate into a deposition chamber, flowing the metal source into the deposition chamber, removing the metal source remaining in the deposition chamber by cutting off the inflow of the metal source and flowing a purge gas into the deposition chamber, cutting off the purge gas and flowing the nitrogen source into the deposition chamber to react with the metal source adsorbed on the semiconductor substrate, and removing the nitrogen source remaining in the deposition chamber by cutting off the inflow of the nitrogen source and flowing the purge gas into the deposition chamber. Accordingly, the metal nitride film having low resistivity and a low content of Cl even with excellent step coverage can be formed at a temperature of 500° C. or lower, and a semiconductor capacitor having excellent leakage current characteristics can be manufactured. Also, a deposition speed, approximately 20 A/cycle, is suitable for mass production.

Patent
05 Jun 2001
TL;DR: An atomic layer deposition (ALD) thin film deposition apparatus including a reactor in which a wafer is mounted and a thin film is deposited on the wafer, a first reaction gas supply portion for supplying a first reactive gas to the reactor, a second reactive gas supply component for supplying another reactive gas at the reactor and an exhaust line for exhausting the gas from the reactor is described in this article.
Abstract: An atomic layer deposition (ALD) thin film deposition apparatus including a reactor in which a wafer is mounted and a thin film is deposited on the wafer, a first reaction gas supply portion for supplying a first reaction gas to the reactor, a second reaction gas supply portion for supplying a second reaction gas to the reactor, a first reaction gas supply line for connecting the first reaction gas supply portion to the reactor, a second reaction gas supply line for connecting the second reaction gas supply portion to the reactor, a first inert gas supply line for supplying an inert gas from an inert gas supply source to the first reaction gas supply line, a second inert gas supply line for supplying the inert gas from the inert gas supply source to the second reaction gas supply line, and an exhaust line for exhausting the gas from the reactor.

Patent
31 May 2001
TL;DR: In this article, a method of forming a thin film using atomic layer deposition (ALD) is provided. But, the method is not suitable for thin films and it requires the use of a single reaction space.
Abstract: The present invention provides a method of forming a thin film using atomic layer deposition (ALD). An ALD reactor having a single reaction space is provided. A batch of substrates is concurrently loaded into the single reaction space of the ALD reactor. Then, a gas containing reactants is introduced into the single reaction space, and a portion of the reactants is chemisorbed on top surfaces of the batch of substrates within the single reaction space. Non-chemically adsorbed reactants are then removed from the single reaction space. In accordance with one embodiment of the present invention, after introducing the gas containing reactants, non-chemically adsorbed reactants are diluted in the single reaction space to facilitate the removal of non-chemically adsorbed reactants.

Patent
15 May 2001
TL;DR: In this article, a metal oxide thin film is deposited on a substrate surface and reduced thereafter essentially into a metallic form with an organic reducing agent using a metal source chemical and an oxygen source chemical.
Abstract: This invention relates to manufacturing of integrated circuits (ICs) and especially conductive layers suitable for use in an IC. According to the preferred method a metal oxide thin film is deposited on a substrate surface and reduced thereafter essentially into a metallic form with an organic reducing agent. The metal oxide is preferably deposited according to the principles of atomic layer deposition (ALD) using a metal source chemical and an oxygen source chemical. The reduction step is preferably carried out in an ALD reactor using one or more vaporized organic compounds that contain at least one functional group selected from the group consisting of —OH, —CHO and —COOH.

Patent
06 Apr 2001
TL;DR: In this article, a method of manufacturing a barrier metal layer uses atomic layer deposition (ALD) as the mechanism for depositing the barrier metal, and the method includes supplying a first source gas onto the entire surface of a semiconductor substrate in the form of a pulse.
Abstract: A method of manufacturing a barrier metal layer uses atomic layer deposition (ALD) as the mechanism for depositing the barrier metal. The method includes supplying a first source gas onto the entire surface of a semiconductor substrate in the form of a pulse, and supplying a second source gas, which reacts with the first source gas, onto the entire surface of the semiconductor substrate in the form of a pulse. In a first embodiment, the pulses overlap in time so that the second source gas reacts with part of the first source gas physically adsorbed at the surface of the semiconductor substrate to thereby form part of the barrier metal layer by chemical vapor deposition whereas another part of the second source gas reacts with the first source gas chemically adsorbed at the surface of the semiconductor substrate to thereby form part of the barrier metal layer by atomic layer deposition. Thus, the deposition rate is greater than if the barrier metal layer were only formed by ALD. In the second embodiment, an impurity-removing gas is used to remove impurities in the barrier metal layer. Thus, even if the gas supply scheme is set up to only use ALD in creating the barrier metal layer, the deposition rate can be increased without the usual accompanying increase in the impurity content of the barrier metal layer.

Patent
24 Sep 2001
TL;DR: A multi-component layer is a dielectric layer formed from a gaseous titanium organometallic precursor, reactive silane-based gas, and a reactive oxidant as mentioned in this paper.
Abstract: A multi-component layer is deposited on a semiconductor substrate in a semiconductor process The multi-component layer may be a dielectric layer formed from a gaseous titanium organometallic precursor, reactive silane-based gas and a gaseous oxidant The multi-component layer may be deposited in a cold wall or hot wall chemical vapor deposition (CVD) reactor, and in the presence or absence of plasma The multi-component layer may also be deposited using other processes, such as radiant energy or rapid thermal CVD

Patent
01 May 2001
TL;DR: An atomic layer deposition (ALD) method employing Si2Cl6 and NH3 as reactants is described in this paper, which includes the steps of placing a substrate into a chamber, injecting a first reactant containing Si2C6 into the chamber, chemisorbing a first portion of the first reaction onto the substrate, removing the non-chemically absorbed portion of this reaction from the chamber and chemically reacting a first reaction with the chemiscorbed first reaction to form a silicon-containing solid on the substrate.
Abstract: An atomic layer deposition (ALD) method employing Si2Cl6 and NH3, or Si2Cl6 and activated NH3 as reactants. In one embodiment, the invention includes the steps of (a) placing a substrate into a chamber, (b) injecting a first reactant containing Si2Cl6 into the chamber, (c) chemisorbing a first portion of the first reactant onto the substrate and physisorbing a second portion of the first reactant onto the substrate, d) removing the non-chemically absorbed portion of the first reactant from the chamber, (e) injecting a second reactant including NH3 into the chamber, (f) chemically reacting a first portion of the second reactant with the chemisorbed first portion of the first reactant to form a silicon-containing solid on the substrate, and (g) removing the unreacted portion of the second reactant from the chamber. In other embodiments, the first reactant can contain two or more compounds containing Si and Cl, such as Si2Cl6 and SiCl4. In another embodiment of the invention, steps b-g are repeated one or more times to increase the thickness of the layer.

Journal ArticleDOI
TL;DR: In this article, a ZnO thin film was deposited on a Si wafer having an oxidized SiO2 layer using a chemical solution deposition process and was applied to a bottom-gate type thin film transistor (TFT).
Abstract: A ZnO thin film was deposited on a Si wafer having an oxidized SiO2 layer using a chemical solution deposition process and was applied to a bottom-gate type thin film transistor (TFT). The films prepared by combined heating at 600° and 900°C exhibited typical enhancement-type TFT characteristics with electrons as carriers. The low heating temperature around 600°C degraded the insulating properties of the SiO2 layer but high temperature annealing recovered that.

Patent
Yanjun Ma1, Yoshi Ono1
08 Feb 2001
TL;DR: In this paper, a multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material, which reduces the effects of crystalline structures within individual layers.
Abstract: A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

Journal ArticleDOI
TL;DR: In this paper, a real-time quartz crystal microbalance method was used to determine the growth rate of TiCl 4/H 2 O ALD at substrate temperatures of 100-400°C.

Patent
03 Oct 2001
TL;DR: In this article, an electrostatic chuck (ESC) was employed to retain the substrate in a process chamber for conducting an atomic layer deposition (ALD) process employing an ECC.
Abstract: A process chamber for conducting an atomic layer deposition (ALD) process employs an electrostatic chuck (ESC) to retain the substrate. RF power is coupled to electrodes in the process chamber to generate ions and reactive atoms for depositing layers on the substrate.

Patent
26 Nov 2001
TL;DR: In this paper, the authors provided methods for forming uniformly thin layers in magnetic devices, including metal oxide layers by multiple cycles of ALD and subsequently reducing the oxides to metal.
Abstract: Methods are provided for forming uniformly thin layers in magnetic devices. Atomic layer deposition (ALD) can produce layers that are uniformly thick on an atomic scale. Magnetic tunnel junction dielectrics, for example, can be provided with perfect uniformity in thickness of 4 monolayers or less. Furthermore, conductive layers, including magnetic 12, 16 and non-magnetic layers 14, can be provided by ALD without spiking and other non-uniformity problems. The disclosed methods include forming metal oxide layers by multiple cycles of ALD and subsequently reducing the oxides to metal. The oxides tend to maintain more stable interfaces during formation.

Patent
20 Jun 2001
TL;DR: A method for manufacturing a zirconium oxide film for use in a semiconductor device by using an atomic layer deposition (ALD) which begins with setting a wafer in a reaction chamber is described in this article.
Abstract: A method for manufacturing a zirconium oxide film for use in a semiconductor device by using an atomic layer deposition (ALD) which begins with setting a wafer in a reaction chamber. Thereafter, a zirconium source material of Zr(OC(CH 3 ) 3 ) 4 (zirconium tetra—tert—butoxide) is supplied into the reaction chamber and then, an unreacted Zr(OC(CH 3 ) 3 ) 4 is removed by a N 2 purge or a vacuum purge. Subsequently, an oxygen source material is supplied into the reaction chamber, wherein the oxygen source material is selected from the group consisting of vaporized water (H 2 O), O 2 gas, N 2 O gas and O 3 gas. Finally, an unreacted oxygen source material is purged out from the reaction chamber.

Journal ArticleDOI
TL;DR: In this paper, the nucleation and growth during tungsten (W) atomic layer deposition (ALD) on SiO2 surfaces was examined using Auger electron spectroscopy (AES) techniques.

Patent
09 Nov 2001
TL;DR: In this paper, an enhanced sequential or non-sequential atomic layer deposition (ALD) apparatus and technique suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, and other conductive, semi-conductive, and nonconductive films was presented.
Abstract: The present invention relates to an enhanced sequential or non-sequential atomic layer deposition (ALD) apparatus and technique suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive films. This is accomplished by providing a non-thermal or non-pyrolytic means of triggering the deposition reaction; providing a means of depositing a purer film of higher density at lower temperatures; providing a means of modulating the deposition sequence and hence the overall process rate; and providing a means of improved radical (176) generation and delivery.

Patent
06 Dec 2001
TL;DR: In this paper, an atomic layer deposition (ALD) method was proposed for forming a silicon nitride spacer by using a first kind of excess gas as a reactant air and thus producing a first mono-layer solid phase of the first reactive air on the wafer.
Abstract: The present invention provides a method for forming a silicon nitride spacer by using an atomic layer deposition (ALD) method. The procedure of the ALD is to use a first kind of excess gas as a reactant air and thus produce a first mono-layer solid phase of the first reactant air on the wafer. When the first chemical reaction is completed, the first excess air is drawn out, and then the second excess air is released to deposit a second mono-layer solid phase of the second reactant air on the first mono-layer solid phase. In this way, a whole deposited layer with a layer of the first mono-layer solid phase, a layer of the second mono-layer solid phase, and so on are stepwise formed on the wafer surface. The ALD method is a time consuming task in deposition process such as in the generation of 0.35 μm to 0.5 μm of VLSI ages. However, in the generation of 0.18 μm, 0.13 μm or beyond of VLSI ages, because the device is getting smaller than ever before, the deposition speed of the ALD method is just right on time to meet the demand and is an appropriate method in depositing silicon nitride spacer.