Patent
Multilayer dielectric stack and method
Yanjun Ma,Yoshi Ono +1 more
TLDR
In this paper, a multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material, which reduces the effects of crystalline structures within individual layers.Abstract:
A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.read more
Citations
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Patent
Atomic layer-deposited laaio3 films for gate dielectrics
Kie Y. Ahn,Leonard Forbes +1 more
TL;DR: In this paper, a LaAlO 3 gate dielectric is formed by atomic layer deposition employing a lanthanum sequence and an aluminum sequence, which is thermodynamically stable and has minimal reactions with a silicon substrate or other structures during processing.
Patent
Dielectric layer for semiconductor device and method of manufacturing the same
Jong-ho Lee,Nae-in Lee +1 more
TL;DR: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the interface layer as discussed by the authors, which consists of metal alloy oxides and metal alloy polysilicon.
Patent
Self-aligned nanotube field effect transistor and method of fabricating same
Joerg Appenzeller,Phaedon Avouris,Kevin K. Chan,Philip G. Collins,Richard Martel,Hon-Sum Philip Wong +5 more
TL;DR: In this article, a self-aligned carbon-nanotube field effect transistor semiconductor device is described, which consists of a carbon-notube, a source and a drain, and a gate.
Patent
Methods for making a dielectric stack in an integrated circuit
TL;DR: In this paper, a high-k dielectric material is sandwiched between two layers of aluminum oxide or lanthanide oxide in the formation of a transistor gate or memory cell.
Patent
Method for making a semiconductor device having a high-k gate dielectric
Mark L. Doczy,Gilbert Dewey,Suman Datta,Sangwoo Pae,Justin K. Brask,Jack T. Kavalieros,Matthew V. Metz,Adrian B. Sherrill,Markus Kuhn,Robert S. Chau +9 more
TL;DR: In this paper, a method for making a semiconductor device is described, which comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer.
References
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Journal ArticleDOI
Structure and stability of ultrathin zirconium oxide layers on Si(001)
TL;DR: In this paper, the structure of ultrathin ZrO2 layers on Si(001) using medium energy ion scattering and cross-sectional transmission electron microscopy was examined.
Patent
Zirconium and/or hafnium silicon-oxynitride gate dielectric
TL;DR: In this paper, a field effect semiconductor device comprising a high permittivity zirconium (or hafnium) silicon-oxynitride gate dielectric and a method of forming the same are disclosed.
Patent
Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same
Yanjun Ma,Yoshi Ono +1 more
TL;DR: In this paper, a high-k dielectric film is provided, which is doped with divalent or trivalent metals to vary the electron affinity, and consequently the electron and hole barrier height.
Journal ArticleDOI
Properties of Ta2 O 5‐Based Dielectric Nanolaminates Deposited by Atomic Layer Epitaxy
TL;DR: In this paper, nanolaminates with improved dielectric characteristics were grown by atomic layer epitaxy, and the films were evaluated by capacitance and currentvoltage measurements, the pure, and films possessed charge-storage factors up to 8, 16, and 19 nC/mm2, respectively, at a leakage current density of 1 μA/cm2.
Patent
Method of providing a dielectric structure for semiconductor devices
TL;DR: In this article, a multi-layer dielectric structure on a substrate includes a primary layer of a metal oxide, which is a high-dielectric constant, and a secondary layer of an oxide or nitride of silicon, on the primary layer, each primary layer being in a first crystalline state characterized by low leakage current.