Showing papers on "Cascade amplifier published in 2018"

Design of Ultrawideband High-Efficiency Extended Continuous Class-F Power Amplifier

Abstract: Total bandwidth of existing wireless communication technologies covers a wide frequency range of over one octave. But most existing power amplifier configurations cannot meet this requirement while at the same time maintaining a high efficiency. Therefore, a new structure that can achieve multioctave bandwidth is proposed in this paper together with the design methodology. The difficulty in realizing a bandwidth larger than one octave lies in the overlapping of fundamental and harmonic frequencies. Regarding this problem, the continuous class-F mode is extended to allow a resistive second harmonic impedance, rather than the pure reactive one. With the relaxed design requirements and overlapping design space of fundamental and second harmonic frequencies, harmonic tuning and fundamental frequency matching networks can be designed separately. More importantly, broadband matching for fundamental frequencies can be implemented simply by considering only three fundamental frequency points using the multiple frequencies matching method. To verify the validity of the proposed methodology, a multioctave power amplifier was designed, fabricated, and measured. Measured results verify a wide bandwidth of 128.5% from 0.5 to 2.3 GHz. Over this frequency range, drain efficiency was larger than 60% with output power greater than 39.2 dBm and large signal gain larger than 11.7 dB.

Direct Automated Quantitative Measurement of Spine via Cascade Amplifier Regression Network

Abstract: Automated quantitative measurement of the spine (i.e., multiple indices estimation of heights, widths, areas, and so on for the vertebral body and disc) is of the utmost importance in clinical spinal disease diagnoses, such as osteoporosis, intervertebral disc degeneration, and lumbar disc herniation, yet still an unprecedented challenge due to the variety of spine structure and the high dimensionality of indices to be estimated. In this paper, we propose a novel cascade amplifier regression network (CARN), which includes the CARN architecture and local shape-constrained manifold regularization (LSCMR) loss function, to achieve accurate direct automated multiple indices estimation. The CARN architecture is composed of a cascade amplifier network (CAN) for expressive feature embedding and a linear regression model for multiple indices estimation. The CAN consists of cascade amplifier units (AUs), which are used for selective feature reuse by stimulating effective feature and suppressing redundant feature during propagating feature map between adjacent layers, thus an expressive feature embedding is obtained. During training, the LSCMR is utilized to alleviate overfitting and generate realistic estimation by learning the multiple indices distribution. Experiments on MR images of 195 subjects show that the proposed CARN achieves impressive performance with mean absolute errors of 1.2496 ± 1.0624 mm, 1.2887 ± 1.0992 mm, and 1.2692 ± 1.0811 mm for estimation of 15 heights of discs, 15 heights of vertebral bodies, and total indices respectively. The proposed method has great potential in clinical spinal disease diagnoses.

Direct Automated Quantitative Measurement of Spine via Cascade Amplifier Regression Network

Abstract: Automated quantitative measurement of the spine (i.e., multiple indices estimation of heights, widths, areas, and so on for the vertebral body and disc) is of the utmost importance in clinical spinal disease diagnoses, such as osteoporosis, intervertebral disc degeneration, and lumbar disc herniation, yet still an unprecedented challenge due to the variety of spine structure and the high dimensionality of indices to be estimated. In this paper, we propose a novel cascade amplifier regression network (CARN), which includes the CARN architecture and local shape-constrained manifold regularization (LSCMR) loss function, to achieve accurate direct automated multiple indices estimation. The CARN architecture is composed of a cascade amplifier network (CAN) for expressive feature embedding and a linear regression model for multiple indices estimation. The CAN consists of cascade amplifier units (AUs), which are used for selective feature reuse by stimulating effective feature and suppressing redundant feature during propagating feature map between adjacent layers, thus an expressive feature embedding is obtained. During training, the LSCMR is utilized to alleviate overfitting and generate realistic estimation by learning the multiple indices distribution. Experiments on MR images of 195 subjects show that the proposed CARN achieves impressive performance with mean absolute errors of 1.2496 mm, 1.2887 mm, and 1.2692 mm for estimation of 15 heights of discs, 15 heights of vertebral bodies, and total indices respectively. The proposed method has great potential in clinical spinal disease diagnoses.

Low-noise amplifier by using a signal-reuse wake-up technology

Abstract: A V-band low-power signal-reuse low-noise amplifier (SRLNA) implemented in 90 nm complementary metal-oxide-semiconductor technology is presented. The proposed SRLNA uses zero- V T and signal-reuse wake-up technologies to improve wake-up sensitivity and reduce power consumption. The SRLNA can be activated or turned off automatically based on the amplitude of the radio-frequency signal power. Time delays of the zero- V T envelope detector and limiting amplifier are analysed in order to loose the constraint on the maximum data-rate. Moreover, the relationship between noise figure (NF), power gain ( S 21 ), input and output return losses ( S 11 and S 22 ) of the SRLNA are discussed in detail, with the quality factors Q nf , Q I , Q in , and Q L defined for NF, S 21 , S 11 , and S 22 parameters derivations. The proposed SRLNA consumes 25 and 12 mW at activate and sleep modes, respectively. The sensitivity of the proposed SRLNA can achieve about -50 dBm.

Design of a CMOS Low-Power Limiting Amplifier with RSSI Integrated Circuit for Low-Frequency Wake-Up Receivers

Abstract: This paper presents the circuit level design of a CMOS low power limiting amplifier with received signal strength indicator (RSSI) for low frequency application. The design utilizes a five-stage cascade amplifier with PMOS double diode-connected load for the limiting amplifier and a successive detection log amp for the RSSI structure. DC feedback technique is employed to suppress the DC offset at the output. The proposed circuit is laid out in $\pmb{0.13 \ \mu}\mathbf{m}$ CMOS technology, then extracted and simulated. It occupies a minimal active area of 0.0084 mm2and is able to operate within a frequency range of 17 kHz to 166 kHz with an RSSI error less than 2dB, while consumes only $\pmb{1.96\mu}\mathbf{A}$ current. It also achieves the −3dB input sensitivity of less than $\pmb{12\mu}\mathbf{V}_{\mathbf{rms}}$ for a typical dynamic range of 81.7 dB, and a maximum settling time of $\pmb{236}\ \pmb{\mu}\mathbf{s}$ . Compared with best performer circuits, our design has the lowest power consumption while other performance aspects are comparable or better.

Sense amplifier driving device

Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, and a sense amplifier. The sense amplifier is connected to the bit line, receives a first control signal, and detects and amplifies a bit line signal of the bit line. The sense amplifier includes a precharge device that is turned on or turned off based on a read control signal, and a transistor output unit that outputs an output voltage based on the bit line signal when the precharge device is turned off.

Circuit and method for bandwidth measurement

Abstract: A circuit for measuring a bandwidth of an amplifier includes a switch-capacitor circuit and a controller. The switch-capacitor circuit is coupled to an output and an input of the amplifier. The switch-capacitor circuit is switchable between a sampling mode and an amplification mode. The controller is coupled to the switch-capacitor circuit and the output of the amplifier. The controller is configured to switch the switch-capacitor circuit between the sampling mode and the amplification mode, control the amplification mode to have various durations, and determine the bandwidth of the amplifier based on the various durations of the amplification mode and corresponding voltages at the output of the amplifier.

Folding cascade amplifier and analog circuit

Abstract: The invention provides a folding cascade amplifier and an analog circuit and relates to the technical field of an amplifier. The folding cascade amplifier comprises a self-adaption bias input stage, apositive feedback nonlinear amplification intermediate stage and a rail-to-rail output stage which are mutually electrically connected. The self-adaption bias input stage comprises a turnover voltagefollower, a bias current mirror, a first differential input pair and a second differential input pair and is used for converting an input voltage signal into a current signal and supplying the current signal to the intermediate stage. The positive feedback nonlinear amplification intermediate stage comprises a first nonlinear current mirror and a second nonlinear current mirror and is used for amplifying the current signal and supplying the amplified current signal to the rail-to-rail output stage. The rail-to-rail output stage is used for converting the amplified current signal into the voltage signal and outputting the voltage signal. According to the folding cascade amplifier provided by the invention, the output current of the input stage can be increased according to square times, the intermediate stage amplifies the current according to the square times again and then outputs the current, the finally output voltage and the input voltage have a biquadrate times relationship, anda slew rate of the amplifier is effectively improved.

Operational amplifier circuit

Abstract: The invention provides an operational amplifier circuit The operational amplifier circuit comprises a recycling folded cascode amplifier, wherein the recycling folded cascade amplifier comprises twofolded tubes, cascode current mirrors and a load capacitor, the grids of the cascode current mirrors are correspondingly connected, each branch of the cascode current mirrors and each of the two folded tubes are respectively in series connection with a first node and a second node, one end of the load capacitor is connected with the first node, and the other end is grounded The operational amplifier circuit further comprises a dynamic acceleration circuit, which is suitable for helping the output voltage of the operational amplifier circuit accelerate to follow the input voltage when an inputvoltage of the recycling folded cascode amplifier jumps from the low level to the high level or from the high level to the low level According to the operational amplifier circuit provided by the invention, due to the additionally arranged dynamic acceleration circuit, the actuating speed of the operational amplifier circuit is largely improved when the static power consumption is not increased

A 13. 8 μW Wake-Up Receiver With 0.4 mVpp Sensitivity For Low Frequency Applications

Abstract: In this paper, a low power low frequency (LF) wake-up receiver was presented. To achieve high sensitivity, a selective amplifier, implemented in an architecture of three-stage fully differential cascade amplifier, utilized neutralization technique and high pass filters to achieve a maximum gain of 50 dB at 125 kHz while maintaining low power. The whole receiver was designed and fabricated in SMIC 0.18 $\mu$m CMOS process with a total size of 0.96 m$\mathrm{m}^{2}$. As a result, the measurements showed that the design achieved a sensitivity of 0.4 mVpp while dissipating just 4.2 $\mu$A from a 3.3 V supply voltage.

Soft fault detection in analog circuits from probability density function

Abstract: A new parametric fault detection scheme for linear and weakly non-linear analog circuits is proposed from probability density function (PDF) of the output. Non-parametric kernel density estimation (KDE) technique is used to estimate the PDF from the random output of the circuit excited with random input stimuli. Two benchmark circuits viz. Continuous-time low pass State Variable Filter circuit and Cascade Amplifier are tested to validate the proposed framework. All the circuits are simulated with CADENCE Virtuoso using UMC-180nm technology. Detectability of the proposed method of soft fault detection is appreciably higher than that of functional test method.

A highly linear wide-band tunable lna for military radio applications

Abstract: A wide-band tunable Low-Noise Amplifier (LNA) was designed to be used in military radios. The LNA works in the frequency range of 30–512 MHz where military walkie-talkies operate. To cover the wide range of operating frequencies, the output of amplifier is divided into four sub-bands with four separate external inductors and integrated capacitor arrays. The first part of the study analyzes the performance parameters such as the gain, tuning, matching, noise figure, and distortion. Layout of the design was completed, and post-layout simulations, including the layout parasitic effects, were run to quantify the performance. The LNA achieves a minimum of 12-dB gain across the entire operating frequency range. The minimum rejections achieved by the LNA at 10% and 20% offset from the center-tuned frequency were 7 dB and 13 dB, respectively. The LNA achieves a worst-case noise figure of 4.6 dB, and the impedance-match parameter (S11) is better than −20 dB under all the conditions. The worst cases P1dB (1-dB Compression Point) and IIP3 (3rd Order Input Intercept Point) were 9.1 dBm and 18 dBm, respectively, across frequency and process–voltage–temperature corners. The design dissipates 20 mA from a 3.3-V power supply and uses a 1.5-V power supply for capacitor array termination.