Showing papers on "CMOS published in 1977"

Analysis and Design of Analog Integrated Circuits

Abstract: The Fifth Edition of this academically rigorous text provides a comprehensive treatment of analog integrated circuit analysis and design starting from the basics and through current industrial practices. The authors combine bipolar, CMOS and BiCMOS analog integrated-circuit design into a unified treatment that stresses their commonalities and highlights their differences. The comprehensive coverage of the material will provide the student with valuable insights into the relative strengths and weaknesses of these important technologies.

CMOS analog integrated circuits based on weak inversion operations

Abstract: A simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p- and n-channel test transistors of a Si-gate low-voltage CMOS technology. Various circuit configurations taking advantage of weak inversion operation are described and analyzed: two different current references based on known bipolar circuits, an amplitude detector scheme which is then applied to a quartz oscillator with the result of a very low-power consumption (<0.1 /spl mu/W at 32 kHz), and a low-frequency bandpass amplifier. All these circuits are insensitive to threshold and mobility variations, and compatible with a CMOS technology dedicated to digital low-power circuits.

Standardized digital logic chip

Abstract: A standardized large scale integrated (LSI) array of standard logic cells on a single complementary metal oxide semiconductor (CMOS) chip. The pattern chosen for the layout of the standard logic cells provides very high cell density and, in combination with the "roadways" provided for power and data interconnects and the availability of "cross unders" within any cell chosen, very high utility ratios of the available cells. The standardized logic chip may be used to implement a large variety of logic circuit designs by the simple expedient of a single custom mask design for the metallization pattern for each unique use.

MOS output buffer circuit with feedback

Abstract: A PMOS output buffer circuit permits interfacing directly with TTL, CMOS, and NMOS. A feedback circuit incorporated into the buffer acts to limit the drive current for negative potential output excursions. The feedback circuit is sensitive to device parameters that vary with processing so that the output characteristics can be set independently of process variables.

CMOS voltage comparator with internal hysteresis

Abstract: A CMOS voltage comparator with internal positive current feedback to achieve a predetermined hysteresis. The voltage level at which the switching occurs is precisely settable. Hysteresis is introduced such that when the set voltage level is exceeded, the output switches quickly and will remain in that state until the input voltage drops by a predetermined hysteresis voltage.

Method of making CMOS structure with retarded electric field for minimum latch-up

Abstract: Method for making CMOS device utilizing a retarded electric field for reducing the current gain in the base region of parasitic transistors in the device. A buried layer is utilized in the base region of the parasitic transistor, and the resistivities of the buried layer and substrate are chosen to reduce both NPN and PNP betas and also to reduce the distributed resistance shunting the P+N and N+P junctions, thereby increasing the level of current required to produce latch-up in the device.

High-density CMOS ROM arrays

Abstract: A single transistor cell and a precharge signal are used to reduce the memory cell area in bulk CMOS ROM arrays to 1.12 mil/SUP 2//bit. Use of SOS/CMOS technology further reduces the memory cell area to 0.38 mil/SUP 2//bit and makes possible CMOS ROMs of up to 32768 bits. Operation of both the array and the decoders is controlled by a precharge signal which is generated internally in a way which is transparent to the user. The CMOS ROMs thus produced are competitive with NMOS ROMs in both density and speed, yet retain all of the advantages of static CMOS circuits such as 1-/spl mu/W power dissipation, full 2.8-15 V voltage operating range, and full -55/spl deg/C-125/spl deg/C temperature range.

Radiation Hardening of CMOS Technologies - AN Overview

Abstract: The current status of four technologies for manufacturing radiation-hardened complementary metal-oxide-semiconductor integrated circuits is presented. The technologies include both aluminum-gate and silicon-gate CMOS structures formed on bulk-silicon and on silicon-on-sapphire (SOS) substrates. The hardness levels achieved on large-scale integrated circuits fabricated in each of these technologies is given. In addition some historical background is included.

CMOS level shifter

Abstract: A level shifter using complementary metal oxide semiconductor (CMOS) transistors is provided. A first transistor couples a first voltage to a node of the level shifter circuit, and the first transistor is controlled by an input signal. A P-channel and an N-channel MOS device are connected in series between the first voltage and a second voltage. The gate electrodes of the P-channel and N-channel MOS devices are connected to the node. An output for the level shifter circuit is taken from a junction formed by the P-channel and N-channel MOS devices. A resistance is coupled between the gate electrodes of the P-channel and the N-channel MOS devices and the second voltage.

Logic circuit using CMOS transistors

Abstract: A logic circuit using CMOS transistors, in which electrical power is supplied to a CMOS logic circuit that is formed of P-channel type and N-channel type MOS transistors by way of a depletion type MOS transistor. The output level with respect to the voltage of the power source that is used is set at some point by the design of the depletion-type MOS transistor.

A charge-balancing monolithic A/D converter

Abstract: The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.

Digital charge-coupled logic (DCCL)

Abstract: A new method of implementing digital logic functions is presented. The method is based on the use of charge-coupled devices in pipeline configurations and results in a very high functional density and an extremely low power dissipation. The authors show how various logic functions such as OR, AND, INVERT, and charge refresh are performed. The operation of a DCCL full-adder is compared with another configuration that uses cascaded dual half-adders and a carry-OR. A floating-gate is required as a binary switch in any function that requires binary inversion such as an exclusive-OR. The switching range of the floating-gate is derived as a function of the gate area, the size of the input charge packet and the extraneous capacitances. The implementation of DCCL pipeline arithmetic is discussed. An 8/spl times/8 multiplier and a 16+16 adder pipeline array now being produced are described. The power dissipation and package density of DCCL are compared with PMOS, NMOS, CMOS, and I/SUP 2/L devices in full-adder configurations and in various size arithmetic arrays. The authors conclude with a description of the present status of the technology and some projections for future uses.

C/sup 2/L: A new high-speed high-density bulk CMOS technology

Abstract: C/SUP 2/L, or closed COS/MOS logic, is a new structural approach to high-speed bulk-silicon COS/MOS logic. C/SUP 2/L is a self-aligned silicon-gate CMOS technology where the gate completely surrounds the drain. The use of such geometry maximises the transconductance to capacitance ratio for devices and thus allows high on-chip speed. The CDP 1802 single-chip 8-bit microprocessor, as well as several memory and I/O circuits announced recently by the RCA Solid State Division, are fabricated in this new technology. Generally, C/SUP 2/L devices show an improvement in packing density by a factor of 3 over standard CMOS and operate at frequencies approximately 4 times faster than standard CMOS. The fabrication sequence for C/SUP 2/L devices requires 6 photomasks (one less than standard CMOS).

A CMOS microprocessor for telecommunications applications

Abstract: THIS REPORT will cover an 8-bit microprocessorX fabricated with a silicon-gate CMOS technology and packaged in a 40-pin DIP. It embodies several architectural innovations and an extended instruction set affording exceptional computing power. Although the fabrication technology is CMOS, it was found that the use of non-complementary structures for certain portions of the logic resulted in a device with the functional density of NMOS, but with power dissipation and internal noise margins approaching that of CMOS. It was recognized early in the development program that an important measure of the computing power of a microprocessor is its efficiency in accessing memory. Accordingly, emphasis was placed on the efficient use of memory. A 16-bit address arithmetic unit (AAU) was provided on-chip to allow address calculations to take place in parallel with data manipulations. To further enhance the computing power, it was decided that the area limitation on the number of user registers which could be implemented on-chip should be avoided by placing all user registers in external RAM, as illustrated in Figure 1. One register set consists of 1 6 16-bit registers. Each register can be used as a 16-bit memory addressing register, a 16-bit accumulator, or an 8-bit accumulator. The source and destination operands of dyadic instructions are pointed to within the register set by an 8-bit DS pointer supplied. as the second byte of the instruction. The DS pointer contains a 4-bit D nibble identifying the destination operand within the register set and a 4-bit S nibble identifying the source operand. The location of the current rcgister set in external RAM is identified by a 16-bit register pointer (RP) maintained on-chip. Since the register pointer is under software control, the location of the register set in external RAM can be changcd on the fly. This makes it possible to form a stack of register sets in RAM, thus saving the current program arguments when executing single or nested subroutine calls. A special instruction allows the programmer to overlap successive rcgister sets by 4,8, or 12 words, thus effecting automatic sharing of 4, 8, or 1 2 arguments between a calling routine and its subroutine. To make efficient use of the large number of user registers available in the external register space, the instruction set provides eight addressing modes for each dyadic instruction and four addressing modes for each monadic instruction. In addition, a novel extension of the instruction set allows up to four distinct sub-modes within each addressing mode, bringing the total number of useablc dyadic modes to 21. Counting the various modes and sub-modes, the processor executes more than 400 unique instructions, some of which require up to 21 successive machine states to complete. Notable among these is a branchon-bit instruction which allows conditional branching on any

Voltage translator for interfacing TTL and CMOS circuits

Abstract: The invention described herein is an interface circuit which effectively allows TTL output voltages to fall within the range of CMOS input thresholds. The interface circuit contains bipolar and FET devices connected to generate an input voltage threshold which is equal to two base-emitter voltage drops. The interface circuit also includes a switching circuit portion which comprises one P-channel MOS transistor connected to one N-channel MOS transistor.

Sense circuit for an MNOS array using a pair of CMOS inverters cross-coupled via CMOS gates which are responsive to the input sense signals

Abstract: The sense circuit includes first and second inverters, connected at their inputs to first and second nodes, respectively. The inverters are selectively cross-coupled by means of transmission gates whose conduction paths are connected between the output of the first and second inverters, respectively, and the inputs of the second and first inverters, respectively. The control electrodes of the transmission gates are coupled to the first and second nodes whereby the transmission gates are turned on and off in response to the voltage levels at the first and second nodes. In the operation of the circuit a precharge voltage, having a polarity and magnitude to turn off the transmission gates, is applied to the two nodes. Subsequently, first and second current signals, having a polarity to generate potentials to turn on the transmission gates, are applied to the first and second nodes, respectively, altering the potentials at the nodes until the transmission gates are turned on. The two inverters are then cross-coupled and latch to either one of two states depending on the difference in the voltage levels at the two nodes. Unlike previously known sense circuits, the need for clock signals to control the conduction at the cross-coupling transmission gates is avoided, since the signals for controlling the conduction of these transmission gates are derived from points within the sense amplifier itself.

MOS-bipolar printer driver circuit

Abstract: In a thermal printer, a print element drive circuit has connected in series a CMOS (Complementary Metal Oxide Semiconductor) inverter gate driving a MOS (Metal Oxide Semiconductor) transistor which in turn drives a bipolar power transistor. The bipolar power transistor provides current pulses to a resistive element which is thermally activated in response to the pulses to cause the printing of characters upon thermal sensitive paper. Character decoding circuitry provides high impedence logic level inputs to the CMOS inverter and these inputs are converted by the printer driver circuitry into corresponding high current drive pulses.

Combined transistor integrated circuit - has N-MOS, CMOS, D-MOS JFET and bipolar transistor on same silicon chip

Abstract: The integrated circuit combines MOSFET, CMOSFET, DMOSFET, JFET and bipolar transistors on the same silicon ship using a sequence of processes so that analog functions can be performed as well as digital. All the components have the same p-type substrate. N-type zones are formed by implantation and diffusion. The insulating regions for the p-channel JFETs and MOSFETs and the collector regions of npn bipolar transistors are formed in these zones.

A 1024-bit, fused link CMOS PROM

Abstract: PROGRAMMABLE read-only memories (PRO%) have been available for several years. Previous fused-link PROMS‘ 3‘ have used bipolar technology with its accompanying high power dissipation. MOS PROMS have used charge storaxe in dualdielectric3 or floating-gate structures. The operating range of these memories is limited by charge loss at elevated temperature^^'^. This paper will describe a fused-link CMOS PROhI which overcomes these earlicr limitations. The basic features are summarized in Table I.

Voltage controlled oscillator

Abstract: A voltage controlled oscillator includes three stages of CMOS inverters arranged in cascade connection. The output of the final stage inverter is connected to the input of the first stage inverter. A capacitor is connected between the input and output of any one of the inverters. The inverter with the capacitor connected thereto comprises two MOS FETs of opposite channel types and is connected in series between high and low voltage sources by control MOS FETs of the same channel types as the respective MOS FETs of the inverter. The gates of the control MOS FETs are connected to control terminals to govern the frequency of the oscillator and one additional fine tune MOS FET is connected across each of control MOS FETs to provide fine tuning of the oscillator.

Integrated circuit device

Abstract: PURPOSE:To reduce power consumption by so combining transistors that the composite structure of pnp and npn transistors operate in a high frequency operating range and a CMOS transistor operates in a low frequency range

High Performance Radiation Hard CMOS/SOS Technology

Abstract: This paper describes the ionizing radiation effects on Si-gate CMOS/SOS short channel devices having channel lengths ranging from 1.8?m to 3.8?m. These short channel CMOS/SOS devices exhibit very high speed performance; the 1.8?m channel length devices achieve a propagation delay time of 0.19 ns at 10V and 0.26 ns at 5V while the 2.8?m channel length devices achieve a propagation delay time of 0.41 ns at 10V and 0.71 ns at 5V. Post-radiation n-channel back leakages of ?0.1?a/mil of channel width and threshold voltage shifts of ? 1V for both n and p-channel devices were obtained after 106 rads (Si) on the 2.8?m channel length devices.

Radiation-Hardened Silicon-Gate CMOS/SOS

Abstract: High performance, radiation hardened silicon gate CMOS/SOS circuits have been fabricated. Radiation hardness was achieved by using a low temperature (875°C), wetprocess gate oxide, and by minimizing the temperature of subsequent process steps. The need for additional temperature steps was eliminated by in-situ doping of the polysilicon gate material with boron and by using ion-implantation instead of diffusions to form source and drain regions. Radiation effects in simple inverter circuits have been measured. Threshold shifts after 106 rads (Si) of ionizing radiation are ?0.5 V for n-channel transistors and ?1. 6 V for p-channel transistors. Irradiation of p-channel transistors in circuit configurations where effective positive gate voltages occur, results in a 4 V shift at 106 rads (Si). Ring oscillator circuits have been fabricated to measure intrinsic circuit performance. With a 15 V power supply, stage delays of 0.5 ns are achieved. These short stage delays verify the suitability of the fabrication process for high speed circuit applications.

Dual depletion CMOS (D/sup 2/CMOS) static memory cell

Abstract: A new type of static memory cell-dual depletion CMOS (D/SUP 2/MOS)-has been designed and fabricated using SOS wafers by the conventional CMOS/SOS technology. In contrast to the conventional CMOS static memory cell, which comprises six transistors, the new cell consists merely of four transistors and one data-line so that the cell area can be significantly reduced.

Output circuit for a digital correlator

Abstract: An analog output circuit for a digital correlator that may be completely integrated with the digital correlator on a single CMOS/LSI chip. The output circuit includes a compensating arrangement so that its output voltage is substantially unaffected by internal processing variables between different chips or by external variables such as temperature or supply voltages. The circuit includes a reference MOS unit and a correlation MOS unit each including parallel arranged PMOS transistors respectively coupled in series with first and second NMOS transistors. An operational amplifier biased to a voltage V REF is coupled between the reference MOS unit and the gates of the first and second NMOS transistors. The circuit operates to bias the gate of the second NMOS transistor so that constant output voltage steps are provided in the series path between the correlation MOS unit and the second NMOS transistor as long as variations of operating parameters track each other uniformly between the PMOS units and between the NMOS transistors.

Establishment of a Radiation Hardened CMOS Manufacturing Process

Abstract: A radiation hardened metal gate CMOS IC process, tolerant to doses in excess of 106 rads (Si), has been established by making necessary modifications to a standard process. These modifications are described, a definition of circuit radiation hardness is discussed, and typical electrical performance characteristics as a function of radiation dose are presented. Procedures are described for assuring the hardness of finished product. Operating life test data indicates that the process is inherently reliable.

Sample and hold circuit

Abstract: A low drift sample and hold circuit is disclosed comprising a transconductance input buffer coupled at its output to a plurality of CMOS inverters through a respective plurality of CMOS switches. The appropriate switches are momentarily addressed by a micro-processor while applying a respective input value to the buffer. The buffer is de-activated prior to the opening of the switch to prevent errors between the sampled and held values.

An Investigation of Flaws in Complex CMOS Devices by a Scanning Photoexcitation Technique

Abstract: A new method is described for using the optical scanner as an inspection instrument for complex CMOS microcircuits. Named the State Superposition Technique, the new method generates a photoresponse image that contains contributions from all active elements in the DUT. Results obtained with CMOS life-test specimens are presented.

Driving circuit of tristate type

Abstract: PURPOSE: To obtain three output terminals while keeping high speed operation, by constituting the circuit with CMOS circuit inputting external selection signal and delivering the input signal and by providing the logic circuit specifying the output with the external selection signal. CONSTITUTION: The circuit is constituted with the CMOS circuit 5 inputting external selection signal to the both input terminals of the bipolar transistor Tr8 of the output inverter circuit using the bipolar transistor as load and MOSFET as driver and of the MOSFET 9, and the CMOS circuit 6 delivering the input signal, and the logic circuits 53,54,63 and 64 which can specify the output are coupled with external selection signal. Thus, the output terminal can take tristate value while keeping high speed operation. COPYRIGHT: (C)1979,JPO&Japio