Showing papers on "Control reconfiguration published in 1975"

An introduction to array logic

Abstract: After a discussion of the reasons for choosing to implement logic in array form. a detailed description of the nature of array logic is given. Topics specifically discussed include general array structures and implementation, influence of decoder partitioning, design of logic arrays, output phase, "split" variables, feedback in logic arrays, and reconfiguration.

The Architectural Elements of a Symmetric Fault-Tolerant Multiprocessor

Abstract: A hybrid-redundant multiprocessor is proposed in which each processing unit and each memory module is triplicated for purposes of error detection and momentary error masking Reconfiguration allows spare units to replace failed units and allows surviving units to regroup after spares have been exhausted. An arbitrary number of processing units and memory modules can be accommodated. A hybrid-redundant bus system interconnects the processors and memories, where the initial redundancy of the buses is a design parameter. A specialized circuit called a bus guardian unit (BGU) is employed in numerous places to control reconfiguration and testing in such a way as to eliminate susceptibility to failure events that occur in one module at a time. Considerable emphasis is placed on dynamic testing. This approach is briefly compared to other fault-tolerant computer systems.

Digital memory with data manipulation capabilities

Abstract: A digital memory comprising a plurality of contiguous circulating serial data storage loops and a plurality of processing elements. Each pair of adjacent loops are coupled to a processing element such that each loop is coupled through two processing elements displaced by one-half loop length. Each processing element includes a serial comparator and a loop control circuit for either isolating or exchanging the data on the two incident loops. Additional circuits are included in each processing element which in combination with the comparator and loop control provide the memory, as the loop data circulates through the processing elements, with the capability of performing an ascending or descending sort of its contents, an associative search of its contents with retrieval of located data, an updating of stored data records, a loading or unloading of a record file or data base and a dynamic reconfiguration of the memory structure.

Feedforward Control of Pure Transport Delay Processes

Abstract: This paper is concerned with the investigation of a feedforward control approach for a class of industrial systems which can be adequately modeled as a pure transport delay. The feedforward control loop is assumed to contain a sensor and actuator both with appreciable dynamics) as well as the feedforward controller. For this class of problems it turns out that application of the standard feedforward control approach leads to controllers which are, from a practical standpoint, unrealizable. The problem arises because the standard approach is based on an attempt to exactly cancel the effects of input disturbances. An alternate design approach is discussed in which a simple and easily realizable controller structure is assumed, and the controller parameters are chosen so that a suitable measure of system performance achieves a satisfactory value. The performance measure used is based on the frequency function relating the input disturbance spectrum to the output spectrum. This approach leads to some simple guidelines for choosing the feedforward controller parameters.

Failure detection and control-system reconfiguration: Past, present, and future

Abstract: The history of failure detection and redundancy management in aircraft applications is reviewed. To date, techniques related to that subject have been based mainly on hardware duplication of like components with failure monitoring and switchover or averaging for redundancy management. Specific examples of these techniques are discussed as they have been applied to the NASA F-8 Digital Fly-by-Wire aircraft and are to be applied to the space shuttle vehicle in the near future.

Will LSI revolutionize communications equipment

Abstract: When gates cost much less than wires, when automatic self-repair is a must, and when power and labor are costly and scarce, then systems design will be different than in the past. Assessed will be the characteristics of post LSI systems which will use time division to save wires, will be serial if possible, switch centered for automatic repair and should make use of microprocessors, even if only for monitoring and reconfiguration.