Showing papers on "Current divider published in 1997"

IC Voltage to Current Transducers with Very Small Transconductance

Abstract: This paper deals with the design of very small ac transconductance voltage to current transducers intended for the design of low frequency continuous-time filters, very large resistors and other applications. The first type of Operational Transconductance Amplifiers (OTA) is based on a triode biased transistor and a current division technique. The second one uses partial positive feedback which allows to reduce transistor dimensions but the sensitivity to transistor mismatches increases. The proposed techniques can be used for the design of high-order low frequency IC filters, ladder or based on biquads, with moderated transistor dimensions while the dynamic range-cutoff frequency performance is comparable to previously reported structures. A 10 Hz third order lowpass ladder filter has been designed with these techniques, and it shows a dynamic range of 62 dB. Besides, a novel biasing technique for capacitive sources coupled preamplifiers is proposed. Experimental results for a prototype, fabricated in a 1.2 μm CMOS process, have shown very low distortion components (THD< 1 level below 15 μ V_RMS and dynamic range of 63 dB. The power consumption is only 10 μwatts and the supply voltages are ± 1.5 volts.

Phase-locked-loop with noise shaper

Abstract: A phase lock loop wherein the reference clock is divided by a variable divider which is capable of dividing the reference clock by a divider ratio of 2, 3, 4, . . . or M depending on the value of a control signal. The control signal is generated from a divider controller in response to a controller input. The noise shaping characteristics of the divider controller results in dithering of the variable divider ratios such that the average frequency of the divided reference clock is at the desired comparison frequency but the quantization noise from the fractional divide is pushed from low frequency to high frequency where it is more easily filtered. The noise shaper can be implemented with many bits of resolution to allow for a wide frequency control range and high frequency accuracy. A dither circuit to prevent limit cycling at the output of the noise shaper.

CMOS voltage regulator with diode-connected transistor divider circuit

Abstract: The voltage regulator of the present invention is configured in a negative feedback operational amplifier loop with diode connected p-MOS devices serving as a resistor divider to reduce the current loading to the voltage multiplier. Each diode connected p-MOS has its own well tied to its source so the VGS (gate to source voltage) of each p-MOS is precisely mirrored across the diode chain by the negative feedback action. This gives a precise voltage at the output of the regulator referenced to a reference voltage VREF. The regulator uses very little current without requiring large value resistors by utilizing the diode connected p-MOS transistors as a resistor divider.

Adjustable cell plate generator

Abstract: A dynamic random access memory device includes a plurality of dynamic memory cells. Each dynamic memory cell is formed at least in part by a cell plate which is connected to a normally fixed reference voltage. The reference voltage is produced by a cell plate generator. The cell plate generator has a first group of voltage divider transistors connected in series from an upper supply voltage source, and a second group of voltage divider transistors connected in series from a lower supply voltage source. The first and second groups of series-connected voltage divider elements form two intermediate voltage divider nodes which are connected to establish the reference voltage. The voltage divider elements are selected to normally establish the reference voltage at a nominal operating value. However, a first bypass transistor is connected around at least one of the voltage divider elements of the first group to selectively bypass it and to thereby raise the reference voltage to a first adjusted testing value which is greater than the nominal operating value. A second bypass transistor is connected around at least one of the voltage divider elements of the second group to selectively bypass it and to thereby lower the reference voltage to a second adjusted testing value which is lower than the nominal operating value.

Driver circuit of light-emitting device

Abstract: A driver circuit of a light-emitting device that is able to reduce the current consumption. This circuit includes a reference current source for generating a reference current, a cascode current source circuit for generating a driving current for the light-emitting device with the use of the reference current, and an input circuit for switching the driving current according to a data signal. The cascode current source circuit has a first current mirror formed by first and second transistors and a second current mirror formed by third and fourth transistors. The first transistor is supplied with a first constant current proportional to the reference current, and controls the second transistor so that the driving current flows through the second transistor. The third transistor is supplied with a second constant current proportional to the reference current, and generates a mirror current with respect to the second constant current. The second mirror current flows through the second transistor as the driving current. The input circuit serves to turn on and off the fourth transistor according to the data signal, thereby controlling the output of the driving current to the light-emitting device.

Digital to analog converter with a reduced resistor count

Abstract: This invention describes a DAC requiring a substantially lower number of resistors for conversion of n+p digital bits. The conversion to an analog signal is done in two voltage dividers. The first voltage divider contains 2 n resistors and is referenced to a voltage bias. The second voltage divider contains 2 p resistors and is referenced to a current bias. The current bias is derived from a current mirror which references the current in the first voltage divider. The use of the current mirror allows all resistors in the DAC to be of the same value which in turn provides an implementation with better accuracy and resistor matching. The number of resistors required to make a conversion of a 12 bit digital signal is 272 where 8 bits are converted in the first voltage divider and 4 bits are converted in the second voltage divider.

High-speed CMOS frequency divider

Abstract: A high-speed CMOS frequency divider is proposed. Using fewer transistors and only NMOS transistors in the regenerative circuits of the latches, the frequency divider achieves higher speed through the reduced capacitances at the output nodes and larger transconductance. A device sizing rule for the maximum input frequency is given. The proposed frequency divider is suitable for high-speed operational while consuming a moderate amount of power.

Bandgap voltage reference circuit

Abstract: A bandgap voltage reference circuit wherein a voltage change is induced across one element to compensate for the temperature-induced voltage change across another element. A stable voltage reference is realized across the series combination of the two elements. The circuit includes an operational amplifier, two transistors, a voltage divider and a non-linear temperature-dependent element. The operational amplifier has two input terminals and an output terminal. The voltage divider includes two resistor in series and is coupled to the operational amplifier output terminal. Each of the transistors has a collector corresponding to one of the operational amplifier input terminals, a base corresponding to one of the voltage divider resistor terminals, and an emitter coupled to a common voltage terminal. The non-linear temperature-dependent element is disposed between the voltage divider output terminal providing the lower voltage and the common voltage terminal. In one embodiment, the non-linear temperature-dependent element is a diode. In another embodiment, the non-linear temperature-dependent element is a bipolar junction transistor. The invention also relates to a method of providing a bandgap reference voltage.

Parallel accumulator fractional-n frequency synthesizer

Abstract: A frequency synthesizer (10) including a synthesizer loop (12) with a fractional-N divider (14), and including a divider control circuit (18) and a combining circuit (22). The divider control circuit (18) provides a variable divide value (20) to the divider (14). The carry values of two accumulators (24, 26) having differing accumulator lengths are applied in parallel to the combining circuit (22). Each of the accumulators (24, 26) provides a portion of a desired fractional divide value (20). The combining circuit (22) also adds an integer divide value (36) to the fractional divide value (16). By coupling the accumulators (24, 26) in parallel, a high frequency resolution with minimal spurious frequencies is achieved, using a simple, low cost circuit.

Low power liquid-crystal display driver

Abstract: A low power digital to analog converter (DAC) circuit is presented that is particularly suited for liquid-crystal display driver systems. The DAC according to one embodiment of the present invention uses a dedicated resistive divider chain that is selectively switched between adjacent pairs of coarse analog reference signals to generate finer analog reference signals. In a preferred embodiment, the resistance of the switches are used in combination with the resistive divider chain to form a voltage divider. In the preferred embodiment, the DAC of the present invention uses MOS transistors to implement the switches and the resistive elements in the divider chain.

Clamping divider, processor having clamping divider, and method for clamping in division

Abstract: A clamping divider has a bit shifter, a multiple accumulator (MAC), and an output circuit. When executing a division with the use of a clamp value of 2 m , the bit shifter shifts one of the divisor and dividend of the division, and the MAC subtracts the shifted one from the other to determine, before calculating a quotient of the division, whether or not a result of the division must be clamped.

Very low gain voltage-controlled oscillator

Abstract: The use of a control circuit (160) with either a programmable divider or divider(s) (190) and multiplexer (200) guarantees that, irrespective of the process variations, a voltage controlled oscillator has a low gain Vin-Fout characteristic in the desired frequency range. Low-gain voltage controlled oscillators are fundamental building blocks of low-jitter phase-locked loop (PLL) systems. The programmable divider/divider(s) (190) and multiplexer (200) are placed at an output of a current controlled oscillator(s) (180). A control circuit (160) defines the optimum current range(s) in the current controlled oscillator(s) (180). In the case of when a programmable divider is used, the control circuit (160) keeps changing the division ratio of the programmable divider until the PLL eventually achieves the "locked" state. When divider(s) and a multiplexer (200) are used, the control circuit (160) keeps changing the selected multiplexer input until the "locked" state has been achieved. Only one current controlled oscillator is achieve at any one time. This control circuit could be for example an auto-lock circuit.

Adjustable voltage divider produced by hybrid technology

Abstract: The invention relates to an adjustable voltage divider arrangement produced by hybrid technology, having a first current-carrying ohmic resistance layer arranged between two printed conductors and a second resistance layer, which is electrically connected to the first resistance layer and to which there is connected a third printed conductor as a pick-off electrode. A cut is made in the second resistance layer for adjusting the voltage divider so that a desired level can be picked off at the pick-off electrode. To be able to pick off very low divider voltages with the required accuracy with only a slight increase in region required by the voltage divider arrangement, it is proposed that the second resistance layer be connected to the first resistance layer over printed conductors in such a way that a first divider voltage tapped at the first resistance layer is applied to the second resistance layer, and a partial voltage of the first divider voltage can be picked off at the pick-off electrode connected to the second resistance layer.

Voltage-controlled reset for logic state initialization

Abstract: A voltage divider and inverter provide a power-on-reset signal. The divider is placed between high and low power voltages, the divided voltage is the input to the inverter and the output of the inverter is the power-on-reset signal. The divider and inverter may be implemented on a single integrated circuit and accompany other, control and operational, circuitry on the integrated circuit. The divider is chosen so that the input to the inverter reaches the inverter's threshold voltage when the power voltage reaches a predetermined value.

Adjustable timer circuit

Abstract: An adjustable timer circuit capable of producing accurate pulse outputs having a wide range of periods. The timer circuit includes a timing capacitor and an associated current source for producing a reference current having a magnitude which is derived from a reference voltage. A current divider is used to divide the reference current down to a smaller current used for charging the timing capacitor. A comparator circuit is provided for comparing the voltage produced across the timing capacitor with a comparison voltage also derived from the reference voltage. The timing capacitor is discharged in response to the comparator output so that subsequent output pulses can be produced. The current divider is adjustable in response to a mode control signal so that different magnitude charging currents can be produced which results in different magnitude pulse width outputs.

Npn bipolar circuit topology for a tunable transconductance cell and positive current source

Abstract: An active filter circuit component includes an all NPN bipolar tunable Gm cell (14) and positive current source (PCS) (12) for supplying common mode current. The tunable Gm cell includes a fixed Gm cell (26) having transconductance Gf, a current divider (28) and a recombination circuit (35) that together effectively multiply Gf by a tuning factor α, where -1 ≤ α ≤ 1, without effecting the cell's common mode current Icm. The PCS includes a pair of unity gain inverting amplifiers (18, 20) that are connected in antiparallel across a pair of matched resistors (R1, R2). Alternately, the resistors can be connected across the inverting and non-inverting sides of a differential amplifier (190). A constant voltage is applied across the resistors to supply Icm, while maintaining a common mode resistance of R/2 and a differential mode resistance approaching infinity.

Current amplifier and current mode analog/digital converter using the same

Abstract: In a current amplifier, a current obtained by holding an input current from an input terminal by a first current sample/hold circuit is added through a connection to a current obtained by inverting the input current by a current inverter to generate a current twice the input current. This current is alternately sampled and held by second and third current sample/hold circuits and alternately output to an output terminal.

Solenoid driver circuit

Abstract: An electrical circuit applies an oscillatory electrical current to a coil of a solenoid in order to cause the solenoid to move in response to a command signal. The circuit includes a signal divider for generating an upper peak current signal value from the command signal and a lower peak current signal value which is a fixed percentage of the upper peak current signal value. A current sense resistor generates a current sense voltage representing current through the coil. A first comparator compares the current sense voltage to the upper current signal value. A second comparator compares the current sense voltage to the lower current signal value. A set/reset flipflop latches a current driver on and off. A current driver applies a driving current to the solenoid coil as a function of output signals generated by the first and second comparators so that the coil current will have a lower peak current value which is substantially a fixed percentage of the upper peak current value.

Phase-locked loop which can automatically adjust to and lock upon a variable input frequency

Abstract: An apparatus is provided for automatically and dynamically adjusting a frequency division factor of a clock divider situated in the feedback loop of a phase-locked loop (PLL). The frequency division factor is modified based on changes in the input signal frequency forwarded to the PLL. If the input signal frequency increases, the decision circuit coupled to the input of the voltage controlled oscillator records that change as an encoded digital signal. That signal will accordingly modify the current frequency division factor dependent on current division factor as well as the current input signal frequency. The decision circuit can be modeled as an A/D converter, and the control unit placed between the decision circuit and the clock divider can be modeled as a state diagram. Each state of the state diagram is indicative of a frequency division factor, or a change in that division factor, wherein the coded digital signal indicates possible change from one state to another. By modifying the frequency division factor, the PLL can dynamically lock upon a changed input signal frequency without varying the clocking signal output from the PLL. Thus, the PLL can accommodate various input signal frequencies yet maintain a relatively fixed clocking signal to be forwarded as a timing reference to a digital processor.

Voltage to current conversion circuit for converting voltage to multiple current outputs

Abstract: This invention provides an absolute value voltage to current conversion circuit which realizes multiple outputs of the current obtained by the conversion of a voltage. For an input voltage of positive polarity, an inverting voltage to current conversion circuit is formed by means of an operational amplifier and a multiple output current mirror circuit. In that case, currents which are 1/n of a converted current are obtained by setting the ratio of the input current to the output current of the current mirror circuit to n:1. For an input voltage of negative polarity, a noninverting voltage to current conversion circuit is formed by means of the operational amplifier and a plurality, n, of bipolar transistors. The converted current is distributed among n bipolar transistors to obtain an output current per transistor which is 1/n of the converted current. As a result, an absolute value voltage to current conversion circuit with multiple outputs can be realized.

Soft switching power converter comprising means for correcting the median voltage of a capacitive voltage divider

Abstract: A power converter comprises two main switches connecting an output either to the positive rail or to the negative rail. Two freewheel diodes for maintaining the current in the load, two snubbers and an auxiliary circuit including an auxiliary inductor in series with two auxiliary switches connected between the output and a mid-point of a capacitive voltage divider supplying a median voltage. Any error of the median voltage relative to its nominal value is evaluated and the main switches are additionally commanded, depending on the direction of the error, for a time period dependent on the amplitude of the error, in order to cause an additional current in the auxiliary circuit to correct the error at least in part.

Phase-locked loop with capacitive voltage divider for reducing jitter

Abstract: In a phase-locked loop comprising a phase detector (1), a loop filter (5) and a controlled oscillator (17) which are arranged on a common integrated circuit, interferences coupled into the substrate of the integrated circuit by other parts of the circuit are suppressed. In a first embodiment of the invention, this object is achieved in that the controlled oscillator (17) is preceded by a capacitive voltage divider (9) which comprises at least two capacitances (10, 12), the controlled oscillator (17) is controlled in dependence upon the output signal of the capacitive voltage divider (9), and the capacitive voltage divider (9), together with the phase detector (1), the loop filter (5) and the controlled oscillator (17) is arranged on an integrated circuit. In accordance with a second embodiment of the invention, the reduction of interference is achieved in that the controlled oscillator (17) has a differential structure and comprises at least two voltage-controlled current sources (18, 19) whose circuits are coupled to a power supply potential and to a substrate on which the integrated circuit is arranged, the controlled oscillator (17) has an output stage (20) which is arranged behind the voltage-controlled current sources (18, 19) and generates two differential digital signals in dependence upon the differential signals applied thereto, which differential digital signals are generated with a high edge steepness by means of switching between two potentials and are applied to amplifier stages (56, 57) which are arranged between power supply potential and reference potential and supply two differential output signals operating at reference potential.

Charge equalising circuit for series-connected elements

Abstract: The circuit equalises charges of series-connected electric or electrochemical cells etc., with a voltage divider coupled in parallel to the series-connected cells such that the number of the divider resistors is the same as that of the cells. A switch is incorporated behind each resistor for the cells. The voltage divider is activated by another switch. Pref. The divider resistors are relays whose contacts connect each the following cell. Alternatively, the divider is formed by ohmic resistors. Self-blocking. FETs, energised by the divider voltage are incorporated in the leads to the cells.

Input ranging circuit for an electronic instrument

Abstract: An input ranging circuit for an electronic instrument that allows for measuring a.c. voltage, d.c. voltage, and d.c. resistance is provided. The voltage ranging circuit has three modes, d.c. volts, a.c. volts, and ohms, which are selected by a mode switch. A resistor network containing an input resistor, feedback resistors, a reference resistor, and divider resistors provides resistances that are ratiometrically scaled to maintain relatively tight ratio tolerances. A switch array coupled to the resistor network provides for the selected circuit configuration and divider ratio in conjunction with the mode switch. Each of the switches in the switch array may be independently controlled via control signals. In d.c. volts mode, the input voltage is divided down according to a desired voltage divider ratio. In a.c. volts mode, the voltage divider is supplemented with an a.c. amplifier configured to extend the useful bandwidth of the input ranging circuit. In ohms mode, a programmable current scaled according to the ratio of resistances in the resistor network is induced through an unknown resistance and the voltage drop is provided at an ohms sense output.

A DELTA-SIGMA ($g(D)$g(S)) MODULATOR HAVING A DYNAMICALLY TUNABLE CONTINUOUS TIME Gm-C ARCHITECTURE

Abstract: A continuous-time tunable Gm-C architecture for a ΔΣ modulator (10) includes a tunable resonator (18) and a low bit, high sample rate quantizer (22) connected in a feedback loop (27). The resonator shapes the quantization noise spectrum so that the bulk of the quantization noise occurs outside the signal spectrum. A tunable Gm cell (30) tunes the resonator's resonant frequency to the signal spectrum's carrier frequency to maximize the modulato's SNR. The tunable Gm cell includes a fixed Gm cell (80) having transconductance Gf, a current divider (82), and a recombination circuit (83) that together effectively multiply Gf by a factor α, where -1≤α≤1, without effecting the cell's common mode current Icm. A positive current source (21a, 21b) supplies Icm, while maintaining a common mode resistance of R/2 and a theoretically infinite differential mode resistance. Thus, the resonator's resonant frequency can be varied from DC to approximately 1 Ghz while maintaining a stable common mode operating point and improving the modulator's quality factor.

Circuit and method for programmably changing the transconductance of a transconductor circuit

Abstract: A programmably variable transconductance circuit (10) and method for varying its transconductance includes first and second current control input devices (16, 18), each having an input (17,19) to which a differential input voltage may be applied. A pair of current steering circuits (26, 28, 30, 32) are each connected in series with a respective one of the first and second current control devices (16, 18) for dividing respective currents in the first and second current control devices (16, 18) between a differential output current path (12, 14) and another current flow path, and a programmable voltage source (90) supplying VCONTROL is connected to control the current division by the current steering circuits (26, 28, 30, 32). The programmable voltage, VCONTROL, is provided by a programmable current control loop (90), which incorporates a master transconductance circuit, to establish a constant transconductance independently of temperature variations. A dynamically controllable resistance, such as an MOS transistor (24), or the like, is connected between the first and second current control input devices (16, 18), and a second voltage source (VGATE) is connected to the dynamically controllable resistance (24) to maintain the dynamically controllable resistance (24) at a constant value.

Sample/hold circuit with current mirror circuits

Abstract: In a sample/hold circuit, a current switch generates a constant current in response to a control signal. A first current mirror circuit receives the constant current to generate first and second currents, and a second current mirror circuit receives the first current to generate a third current. A voltage buffer receives an input voltage at an input terminal to generate an output voltage at an output terminal. The voltage buffer is activated by the second and third currents. A hold capacitor is connected to the output terminal.

A DELTA-SIGMA ( DELTA SIGMA ) MODULATOR HAVING A DYNAMICALLY TUNABLE CONTINUOUS TIME Gm-C ARCHITECTURE

Abstract: A continuous-time tunable Gm-C architecture for a DELTA SIGMA modulator (10) includes a tunable resonator (18) and a low bit, high sample rate quantizer (22) connected in a feedback loop (27). The resonator shapes the quantization noise spectrum so that the bulk of the quantization noise occurs outside the signal spectrum. A tunable Gm cell (30) tunes the resonator's resonant frequency to the signal spectrum's carrier frequency to maximize the modulato's SNR. The tunable Gm cell includes a fixed Gm cell (80) having transconductance Gf, a current divider (82), and a recombination circuit (83) that together effectively multiply Gf by a factor alpha , where -1

Frequency-independent voltage divider

Abstract: A frequency-independent voltage divider comprises a series arrangement of resistors (R1-RM+1) connected between an input terminal (2) and a reference terminal (1) for receiving an input signal (Vi). An output terminal (3) for supplying an output signal is coupled to a tap of the series arrangement. The influence of parasitic capacitances (CP1-CPM+1) is eliminated by means of compensation capacitors (CCMP1-CCMPM).