Showing papers on "Digital electronics published in 2023"

Speed and Scalability of Ambipolar Deep-Subthreshold TFTs for Ultralow-Power Printed Electronics

Abstract: This work evaluates the speed and scalability potential of ambipolar deep-subthreshold printed-carbon-nanotube thin-film transistors (CNT-TFTs) for the design of ultra-low-power CMOS-like circuits. Transistor and circuit simulations are developed based on experimental device measurements. Our simulations allow the assessment of this emerging printed electronics technology in terms of speed, energy/power consumption and scalability to digital circuits of progressively higher transistor count including elementary logic gates, ring-oscillators and other representative digital circuits. It is shown that digital circuits based on this technology are compatible with propagation delays ≤ 1 ms per NOT logic gate, while operating at ultra-low supply voltages (0.2 V) and with ultra-low static power dissipation (1 pW). Finally, this study develops Monte Carlo simulations to assess the impact of device parameter variations on the viability of large-scale circuit integration based on ambipolar deep-subthreshold printed-CNT-TFTs.

An Energy-Aware Nano-Scale Design of Reversible Atomic Silicon based on Miller Algorithm

Abstract: Atomic silicon and reversible logic are domain field-coupled nanocomputing (FCN) techniques that have drawn significant attention for their lower power consumption, area, and design overhead. As atomic silicon and reversible logic reach dramatically reduced occupied area and power consumption, they can be a suitable alternative to CMOS technology. These technologies can significantly reduce the occupied area and energy consumption in all kinds of digital circuits, which are the two most challenging aspects of developing digital circuits. On the other hand, the Miller algorithm is a crucial synthesis for suggesting reversible circuits with extraordinary techniques in nanotechnology. It is an exceptionally effective and systematic method based on quantum rules for designing and proposing reversible circuits that can help suggest a reversible gate with low energy and a low occupied area. This study aims to construct novel nano-scale circuits with a focus on low-occupied area and minimal energy consumption as essential factors while designing digital circuits. In this paper, we propose a reversible gate with the well-known Miller algorithm and atomic silicon technology. Then it is used to develop a reversible full adder, 4-bit ripple carry adder, and 4:2 compressor. Finally, the proposed structures are simulated using the SiQAD tool.

Electronics

Abstract: The material of module 2 "Electronics" is systematically presented in accordance with the modern university program of the discipline " Electrical Engineering and Electronics" for non-electrotechnical areas of training of bachelors and certified specialists. The element base of semiconductor electronics devices is considered: classification, voltage and frequency characteristics, features of the use of electronic devices in various operating modes are given. The principles of construction and functioning of typical analog, pulse and digital devices are described in detail. A separate chapter is devoted to the principles of converting light energy into electrical energy and vice versa, the design and operation of optoelectronic devices and fiber- optic lines of information transmission. Meets the requirements of the federal state educational standards of higher education of the latest generation. For students of higher educational institutions studying in non-electro- technical areas of bachelor's and graduate training.

Mocast 2021

Abstract: The 10th International Conference on Modern Circuit and System Technologies on Electronics and Communications (MOCAST 2021) will take place in Thessaloniki, Greece, from July 5th to July 7th, 2021. The MOCAST technical program includes all aspects of circuit and system technologies, from modeling to design, verification, implementation, and application. This Special Issue presents extended versions of top-ranking papers in the conference. The topics of MOCAST include:

Analog/RF and mixed signal circuits;
Digital circuits and systems design;
Nonlinear circuits and systems;
Device and circuit modeling;
High-performance embedded systems;
Systems and applications;
Sensors and systems;
Machine learning and AI applications;
Communication;
Network systems;
Power management;
Imagers, MEMS, medical, and displays;
Radiation front ends (nuclear and space application);
Education in circuits, systems, and communications.

Efficient Processing Time with Carry-lookahead Adder Memristor Rationed Logic

Abstract: This paper presents a novel approach to the design of full adder circuits, leveraging the unique properties of memristors and CMOS logic in a hybrid system. This paper explores the design and operation of memristor-based logic gates, including AND, OR, NAND, and NOR gates, realized through CMOS inverters. This paper further proposes a full adder circuit using Hybrid Memristor-CMOS logic and a carry look-ahead adder (CLA). Our simulations demonstrate that the proposed full adder circuit outperforms traditional RCA-based circuits in terms of speed. This work contributes to the ongoing discourse in digital electronics, offering fresh perspectives and potential solutions to existing challenges, and hope it will inspire further research in the field of memristor-based digital electronics.

Implementation of Full Adder Using Nand Gates

Abstract: : In digital electronics, there are different types of logic circuits used to perform different kinds ofarithmetic operations. One of them is adder. Adder (or Binary Adder) is a combinational logic circuit that performs the addition of two or more binary numbers and gives an output sum. There are two types of adders present namely, half adder and fulladder. Since, adder are logic circuits, thus they are implemented using different types of digital logic gates such as OR gate, AND gate, NOT gate, NAND gates, NOR gates, etc. In this article, we will discuss the Full Adder Realization using NAND Gates. But before that let’s have a look into the basics of full adder.

DeepSPICE: Accelerating Digital Cell Characterization Using Deep Learning

Abstract: This paper introduces DeepSPICE, a machine learning approach to accelerate the characterization of the building blocks, or cells, of digital integrated circuits. In contrast to the current approach of computing the input-to-output propagation delays of a cell by simulating all possible input event combinations, DeepSPICE employs a Deep Neural Network (DNN) to learn from the propagation delays obtained by simulating a small subset of input event combinations and to predict those for the rest. The DNN for training and prediction is created using the Keras framework, and Python is used for automating the entire flow. The effectiveness of the DeepSPICE approach is demonstrated on 14 CMOS logic cells with the number of inputs ranging from 2 to 7. Simulations to create the training set for each cell are performed using the open source NGSPICE circuit simulator on their transistor-level circuit descriptions. Experiments using two different train:test ratios of 0.25:0.75 and 0.3:0.7 demonstrate the promise of reduction in time with DeepSPICE, especially for large cells where simulation costs are expensive. For cells with at least 6 inputs, DeepSPICE computes propagation delays for all input event combinations 2 to 2.2 times faster than baseline while limiting the error between 6.3% and 12.3%.

Variable Ordering in Binary Decision Diagram Using Spider Monkey Optimization for Node and Path Length Optimization

Abstract: Binary Decision Diagrams (BDDs) are an important data structure for the design of digital circuits using VLSI CAD tools. The ordering of variables affects the total number of nodes and path length in the BDDs. Finding a good variable ordering is an optimization problem and previously many optimization approaches have been implemented for BDDs in a number of research works. In this paper, an optimization approach based on Spider Monkey Optimization (SMO) algorithm is proposed for the BDD variable ordering problem targeting number of nodes and longest path length. SMO is a well-known swarm intelligence-based optimization approach based on spider monkeys foraging behavior. The proposed work has been compared with other latest BDD reordering approaches using Particle Swarm Optimization (PSO) algorithm. The results obtained show significant improvement over the Particle Swarm Optimization method. The proposed SMO-based method is applied to different benchmark digital circuits having different levels of complexities. The node count and longest path length for the maximum number of tested circuits are found to be better in SMO than PSO.

Noise–dissipation relation for nonlinear electronic circuits

Abstract: An extension of fluctuation–dissipation theorem is used to derive a “speed limit” theorem for nonlinear electronic devices. This speed limit provides a lower bound on the dissipation that is incurred when transferring a given amount of electric charge in a certain amount of time with a certain noise level (average variance of the current). This bound, which implies a high energy dissipation for fast, low-noise operations (such as switching a bit in a digital memory), brings together recent results of stochastic thermodynamics into a form that is usable for practical nonlinear electronic circuits, as we illustrate on a switching circuit made of an nMOS pass gate in a state-of-the-art industrial technology.

An RTL-to-GDSII Flow for Single Flux Quantum Circuits Based on an Industrial EDA Toolchain

Abstract: Josephson Junction-based superconducting circuits are promising candidates for high-speed digital electronics with dramatically lower power consumption than CMOS, as well as a potential enabler towards the implementation of large-scale quantum computing. In this paper, we will describe an automated flow for the creation of microcontrollers and other digital systems in the single flux quantum (SFQ) technology. Starting with a register-transfer level (RTL) description of the circuit, the flow integrates logic synthesis, technology mapping, timing and logic verification, library cell placement and routing, and completes with a candidate physical design for fabrication. The flow makes use of the same tools employed in leading-edge CMOS. We will examine the challenges specific to the SFQ technology at the different stages in this flow. We will also report on metrics to qualify the resulting physical layout, such as circuit density and timing results.

Comprehensive Study on State of Art Energy Efficient Voltage Level Shifters for Multi-VDD Systems

Abstract: In both analogue and digital systems, the Level Shifter (LS) circuit has emerged as a crucial circuit element. Research papers towards the advancement of LS circuits have multiplied during the last few decades. their applications as well as their performances. As a result, this review article offers an in-depth analysis of the Level shifter design, covering circuit design features as well as several design approaches like testing approach, size methods, layout design process, and circuit evaluation methodology. This study evaluates the most modern LS circuits and to provide performance measurements for them in the last section.

Improving Robustness of Two Speed Serial Parallel Booth Multiplier Using Fault Detection Mechanism

Abstract: When it comes to circuit design, digital elements have a pivotal and crucial impact. Input values given to these components can be degraded by internal and external disturbances, it can happen either by virtue of foreign factors, to the lack of efficiency in the sensors, or maybe due to unknown lags in the communication systems. Hence, it is vital when the output responses related to these devices stay as robust when slightest fluctuations occur. Layout of robust components has been reported as primary challenge in the implementation of electronic systems. Ways to improve the robustness of circuits have been dealt with but either by adding huge amount of extra logic, alter the circuit latency, or these are suitable only for such circuits like microprocessors. Also, they suffer limitations by capturing application particular information of the circuit. However, the proposed methodology requires only a small increment in the extra hardware, which only affects the timing characteristics of the circuit in a less considerable manner, and will spontaneously apply to any of the circuits which are arbitrary.

Digitize the Human Body by Backscattering Based Nano-Tattoos: Battery-Free Sensing

Abstract: Artificial intelligence (AI) lead a new era in remote health monitoring and preventive care, by making wearable electronics, specifically electronic skin, monumental in the future of healthcare. However, remote data collection from these sensors still largely relies on external circuits such as amplifiers, analog to digital converters, and batteries. This extra layer of circuity results in bulky systems, which greatly limits the application of these sensors and forces them to only work at certain places on the human body for limited time, such as only wrist. Here, we present an original technique for producing ink-based nano-tattoos that can be applied anywhere on the human body in various shapes and sizes and transmit data without requiring any external circuit elements, including batteries, by utilizing backscattering communication principles. Ink of nano-tattoos based on ZnO nanowires embedded in graphene aerogels can analyze and track quality of human body movements anywhere there is an ambient wireless signal and a smart phone. This method turns every surface into a potential sensor, digitizing the human body.

An Automated Static CMOS Schematic Generation Using MATLAB

Abstract: Nowadays, demands of integrated circuits (IC) increase day by day for many industries applications. The transistors count per IC also increases according to Moore’s law to speed up the process. The power consumption of IC is more due to huge transistors count. Digital circuits are one of a major part in ICs. There are varieties of method discussed to reduce the power consumption of digital circuits. Few are using less operating voltage, clock gating, multiple voltage levels and etc. In this paper we suggested to reduce the power consumption of digital circuits in IC by directly getting the equivalent CMOS circuits instead of standard cells. By this method, we can reduce the required transistors count for digital circuits design. We have written MATLAB program plotting static CMOS circuit directly for Boolean function, because none of the tool gives static CMOS circuit automatically.

Optimization And Power Delay Analysis of Different Full Adder Circuits

Abstract: An arithmetic circuit is made up of several adders. A digital system’s overall performance is significantly influenced by the performance of an adder. High care must be used when creating these adder cells because any alteration to the adder cell would reduce the overall performance of the intended circuit. Therefore, even little power savings result in significant power savings and improved circuit performance. In order to reduce power consumption with high-speed operation, a number of strategies are put into place as the technology is progressively scaled down. The numerous complete adder circuits have been examined in this work. The power usage and transistor count of the simulation results generated with Micro wind are compared. These performance results will facilitate the circuit designer to settle on right adder for their required application need.

Front-Line Research on “Cryogenic Digital Circuits for Peripheral Circuits of Quantum Computer”

Abstract: Research on quantum computers is actively carried out all over the world due to their high computing performance utilizing quantum superposition states in quantum bits (qubits). Currently, qubits based on solid-state devices using superconductor or silicon devices are the most promising because of its controllability and scalability. These devices are usually placed at cryogenic temperatures, around several mK, to reduce the thermal noise for the qubit. One obstacle for these systems is the necessity of a large number of control and readout microwave lines to connect the qubits with room temperature electronics. To overcome this issue, much research on cryogenic interface circuits to connect qubits and room-temperature electronics has recently proceeded. The investigative committee of the Institute of Electrical Engineers of Japan investigated the front-line research on this topic. In this paper, we summarized the investigation results.

Erasable and Field Programmable DNA Circuits Based on Configurable Logic Blocks

Abstract: Abstract DNA is commonly employed as a substrate for the building of artificial logic networks due to its excellent biocompatibility and programmability. Till now, DNA logic circuits have been rapidly evolving to accomplish advanced operations. Nonetheless, the process of creating DNA logic circuits according to personal needs (logical truth table) requires extensive knowledge on digital circuits. Moreover, even after the researchers endeavor to build a DNA circuit, it lacks field programmability and thereby being disposable and inconvenient. Herein, inspired by the Configurable Logic Block (CLB) paradigm in silicon digital circuits, we present the CLB-based field-programmable DNA circuit that uses clip strands as its operation-controlling signals. It substantially simplifies the construction of desired circuits by establishing the relationship between circuits and operation-controlling strands. Additionally, the field programmability enables users to realize diverse functions with limited hardware. We firstly constructed CLB-based basic logic gates (OR and AND), and effectively demonstrate their eras ability and field programmability. Furthermore, by simply adding the appropriate operation-controlling strands, we achieved multiple rounds of switch among 5 different logic operations on a single two-layer circuit. In addition, we successfully built a circuit to implement two fundamental binary calculators: half-adder and half-subtractor, proving that our design could imitate silicon-based binary circuits. Finally, we built a comprehensive CLB-based circuit that enabled multiple rounds of switch among 7 different logic operations including half-adding and half-subtracting. Overall, the CLB-based field-programmable circuit greatly streamlines the process to build DNA circuits and immensely enhances their practicability. We believe our design could be widely used in DNA logic networks due to its efficiency and convenience.

Design and Testing of Digital Logic Gates Using HCS Macro-Model

Abstract: Single Electron Transistor (SET) has become very popular in industry as well as in academia. As SET can control the tunneling of electrons one by one through the channel so that power dissipation is very low as compared to conventional Complementary Metal Oxide Semiconductor (CMOS), though it has high speed, high gain like properties. So, the hybridization of CMOS with SETcan be used in modern Very Large Scale Integration (VLSI) circuit design, and this technique is very popular as Hybrid CMOS–SET (HCS) which uses less power with high speed of response. But the model requires two distinct simulators, such as, Simulation Program with Integrated Circuit Emphasis (SPICE) for CMOS and SIMON or Korea Single Electron Circuit Simulator (KOSEC) or Monte Carlo Single Electronics Simulator (MOSEC) or Single-Electron Nano Electronic Circuit Analyzer (SENECA) for SET, to simulate a single HCS model. To overcome this problem of HCS, macro- modelling of SET has been introduced by different researchers which can be simulated by using MATLAB with SIMULINK, SPICE and so on. In this present paper, macro model of SET has been incorporated with CMOS so that it can be simulated using a single software and this technique has been used to develop different logic circuits and the output can be controlled by the individual components of SET macro model. The simulation results show that the proposed model also consumes low power (0.275 nW to 0.55 nW) with high speed which can be used in VLSI design.

Analysis of High Performance Low Power Full Adder Circuit

Abstract: Over the past few decades, the electronics sector has experienced significant growth. This is all a result of the development of nanotechnology. The advancement of nanotechnology has allowed for the creation of numerous high-speed microelectronic devices that rely on sophisticated computer techniques to maintain their accuracy and effectiveness. With the advent of very large-scale integration (VLSI) designs, the application of integrated circuits (ICs) in high-performance computing systems, telecommunication devices, video and image processing algorithms, control systems and consumer electronics has substantially risen. The most basic element needed for all this processing and computation is the complete adder. A full adder circuit is a crucial part of arithmetic and logic units (ALUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), and a huge variety of different digital systems and circuits. Greater speed, longer battery life, and other qualities are in higher demand as technology advances. Today, creating complete adder circuits that satisfy the expanding demands is one of the biggest challenges facing VLSI architects. Thus, this research survey has covered the prospective technologies that are currently accessible. With the help of this study, the paper intends to provide a comparative analysis of the available architectures and facilitates to come up with a decision on the one that produces the most beneficial outcomes.

Implementation of Digital Applications Using Efficient CML based designs

Abstract: This paper implements various digital applications of available efficient CML based designs. These digital applications can be used in mixed-signal processing blocks wherein high performance is required. These circuits have been implemented from the available efficient designs such as MTT cell based XOR gate, Quad Cell based XOR gate and MCML and PFSCL based tri-state circuits. Various digital applications wherein these designs are cascaded have been implemented such as 4-Bit RCA, 2:4 Decoder and Linear Feedback Shift Register (LFSR). Further, layouts of efficient CML designs have also been implemented in this paper.

A Simple Stuck-at-faults Detection Method in Digital Combinational Circuits

Abstract: This paper considers the new method of detection (diagnostic) stuck-at-faults (0/1) in digital combinational circuits based on a numerical set-theoretical approach. Compared to known methods and algorithms, the proposed approach differs in simpler implementation of searching for vectors of test codes at arbitrary points of the studied logic circuit. A few simple set-theoretical operations and procedures are sufficient to determine the location and the type of a stuck-at-fault (0/1). This is evidenced by the presented examples of application of the proposed method, that are borrowed from the publications of well-known authors.

Practical Implementation of an Analogue and Digital Electronics System for a Modular Cosmic Ray Detector—MCORD

Abstract: A Modular COsmic Ray Detector (MCORD) was prepared for use in various physics experiments. MCORD detectors can be used in laboratory measurements or can become a part of large measurement sets. MCORD can be used as a muon detector, a veto system, or a tool supporting the testing and calibration of other detectors. MCORD can also work as a stand-alone device for scientific and commercial purposes. The basic element of MCORD is one section consisting of eight oblong scintillators with a double-sided light reading performed by silicon photomultipliers (SiPMs). This work presents a practical description of testing, calibration, and programming of analogue and digital electronics modules. The characterisation and calibration methods of the analogue front-end electronic modules, the obtained results, and their implementation into an operating system are presented. In addition, we describe the development environment and the procedures used to prepare our kit for practical use. The architecture of the FPGAs is also presented with a description of their programming as a data-collecting system in a simple coincidence circuit. We also present the possibilities of extending the data analysis system for large experiments.

Miscellaneous: Linear IC Applications, Logical Gates

Abstract: In this chapter, we will discuss some practical and useful applications of the linear integrated circuits (mainly op-amps) and some mostly used logic gates. Some typical circuits are mentioned, like a stereo mixer and sound generator. The logic digital circuits are discussed, including the NOT, AND, OR, NAND, NOR and XOR. The flip-flop circuit is explained. Applications like the binary counter and binary adder are described.

Memristor-Inspired Digital Logic Circuits and Comparison With 90-/180-nm CMOS Technologies

Abstract: Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and 2 $\times$ 1 mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density Y $_{\text{2}}$ O $_{\text{3}}$ -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.