Showing papers on "Digital signal published in 1973"

Device for monitoring the operating parameters of a dynamic system

Abstract: The device for monitoring the operating parameters of a dynamic system (for example, an aircraft having an internal combustion engine power plant) comprises a plurality of sensors each one of which is adapted to measure the magnitude of a specific operating parameter and to generate a sensor signal voltage that varies directly with the magnitude of the operating parameter. The sensor signal voltage generated by each sensor is transformed to a conditioned and calibrated analog signal voltage the magnitude of which is in the same proportion to a predetermined reference voltage as the actual magnitude of the operating parameter being measured is to a predetermined reference magnitude of the operating parameters. The conditioned analog signal voltage gradient is divided into a predetermined number incrementally increasing analog signal voltage increments, and analog signal voltage increment indicator means are provided for visually indicating the analog signal increment that corresponds to the actual magnitude of the operating parameter being measured. Selector switch means are provided for selecting the conditioned analog signal that corresponds to a particular one of the operating parameters being measured. The selected conditioned analog signal is converted to a corresponding multibit digital signal which is transmitted to an array of alpha-numeric visual display units which display in numeric form the actual magnitude of the particular operating parameter being measured.

Feed-forward, error-correcting systems

Abstract: In a feed-forward, error-correcting system in accordance with the present disclosure, the error signal is formed by comparing the modulation component of the signal before and after signal processing. The error signal is then used to modulate the main signal so as to reduce the modulation error components introduced by the signal processing circuits.

Digital cryptographic system and method

Abstract: The specification discloses a digital cryptographic system operating under a digital coding scheme having forbidden control characters with common bit characteristics. In the encoding mode, clear digital data and randomized digital data are stored and selected bits of the clear and randomized digital data are modulo-2 added. The added bits are then examined to determine whether or not the bits have the common bit characteristics of the forbidden control characters. If so, the selected bits of the stored clear digital data are varied to prevent the subsequent generation of forbidden control characters in the encoded data. The clear digital data and randomized digital data are then modulo-2 added to generate encoded data. The present system is compatible with eight-level digital codes and the system includes parity bit checking techniques to ensure accuracy of operation. The present system may be operated as either an On-line or Offline system and may be utilized to provide security of digital transmission between teleprinters or between a teleprinter and a digital computer or the like.

Bisitable digital circuitry

Abstract: Bistable digital circuits including cross coupled gates having complementary inputs provided by CMOS threshold circuits coupled to a common digital signal input. Complementary unbalanced transfer characteristics of the threshold circuits provide widely separated high and threshold voltages approaching respective high and low supply potentials. The coupling between gates maintains the bistable digital circuits in a given stable state until the high and low threshold voltages are crossed over in response to a change in logical level at the signal input.

Asynchronous internally clocked sequential digital word detector

Abstract: A detector for detecting predetermined digital words within a train of signals wherein the digits in the words each have a predetermined time period. The detector continuously samples the train of signals coupled thereto. Samplings are taken a number of times during the interval of a digit time period, and a digital signal corresponding to the sampled signal for each sample taken is stored in a multi-stage storage register. Comparison circuitry compares the digital signals in the storage register with a first predetermined word in a memory circuit. If there is a correlation, the comparison circuit counts for a time period long enough to sample the train of signals and store a new series of signals corresponding to a second digital word. The comparison circuit compares these second digital signals with a second word in the memory circuit. A correlation between theset two words produces a detection signal.

Control system and devices for internal combustion engines

Abstract: To control at least one solenoid operated fuel injection valve in dependence upon the rate of air flow, and particularly to avoid interference with stray signals generated in the electrical system associated with an internal combustion engine, an air flow meter is arranged in the induction pipe of the engine which has an output providing signals in digital form, for example by controlling the frequency of an osciallator which is then converted into digital signals by a frequency/digital converter. The digital signals are applied to a computing circuit which includes a digital differential analyzer and an interpolator, or function generator which is connected therein and so set that it simulates the operating characteristics of the internal combustion engine to modify the digital signal and provide an output which can be converted by a frequency/time converter to a timing signal to control the solenoid of the fuel injection valve and open the fuel injection valve for a predetermined period of time, depending on rate of air flow, or other engine parameters, and as adjusted for the operating characteristics of the engine over its operating range.

Video signal transmission system

Abstract: A video signal transmission system for transmitting a video signal with its band width being compressed. On the transmitting side, there is provided a synchronizing signal generator for generating a horizontal synchronizing signal and a picture element clock signal. A regularly selective transmitter supplied with the output from the synchronizing signal generator to selectively remove picture elements of the video signal with a predetermined frame period. Thus, the video signal is formed into a plurality of sequences, which are and sequentially transmitted. On the receiving side, there is provided a synchronizing signal generator for generating a horizontal synchronizing signal and a picture element clock signal synchronized with those on the transmitting side, a frame memory for storing the video signal of one frame, and a movement detector for comparing the video signal sequence transmitted from the transmitting sides with those video signal sequences stored in the frame memory to determine whether the video signal of the transmitted sequence belongs to a moving picture or to a stationary picture and to produce a signal in accordance with the result of the comparison, the transmission station has no frame memory. The movement detector is included in the receiving station, therefore there is no need of transmitting a movement detecting signal.

Bandwidth compression system and method

Abstract: A method and apparatus is disclosed for converting a wide-bandwidth signal to a narrow-bandwidth signal, the disclosed method and apparatus being particularly well suited for converting a wide-bandwidth real-time television signal to a narrow-bandwidth signal. A sampled video signal is coupled to an analog-to-digital converter which converts the amplitude of each sampled element to a binary code word having a predetermined number of bits. The binary code words are then written into a buffer storage element controlled by a clock switching device and later clocked out of the buffer storage device at a clock rate less than the input rate with the output from the buffer storage device being coupled to a digital-to-analog converter whose output is an analog signal with the same amplitude variations as the sampled video signal but with a time base stretched out by a predetermined factor. The field, either odd or even interlace, from which the sampled video signal was taken is identified by ascertaining the location of the horizontal signal pulses relative to the vertical signal pulse, and this field index may then be used to code the output narrow-bandwidth video signal. Another embodiment is disclosed which utilizes an analog shift register as the buffer storage device in place of the digital buffer storage with its attached analog-to-digital and digital-to-analog converter. An alternate embodiment is disclosed which utilizes a pair of parallel connected buffer storage units (either digital or analog) controlled by output gating to provide for a continuous non-interlaced narrow-bandwidth signal.

Arrangement for a columnar display of variation gaging signals

Abstract: An arrangement is disclosed producing a columnar display of variation data developed during workpiece gaging operations, including electrical gaging transducers for sensing dimension variations at points on surfaces of a workpiece, an analog to digital converter converting electrical analog gaging signals to digital form, and also including a digital computation network which may be selectively set to compute either the variation in each of a number of gaging signals each produced by an individual gaging transducer, or the maximum variation occurring in all of these individually produced gaging signals, or the difference between the minimum and maximum values of all of the gaging signals produced. These computed values are outputted in the form of digital signals which are decoded so as to activate individual indicator elements in a vertical series of electrically activated indicator elements, with a single indicator element activated in the series for each digital signal level such that the relative vertical position of the activated indicator element corresponds to the relative level of the digital signal to yield a columnar display of the variation data described.

Detection of digital data using integration techniques

Abstract: Data represented in digital signals are detected by integration techniques; each integration occurs over the entire detection or sample period. Recovery of each integration circuit occurs in a subsequent sample period. A pair of integration circuits forming one integrator are provided for each state of the digital signal with the integrators being alternately actuated. In a two-state signal, two integrators are provided; each integrates during a different signal state. To determine data contained in the signal, an amplitude comparison is made between the output of the analog-OR of each integrator of the several signal states. Also disclosed is an extremely sensitive comparator latch which utilizes the high gain of a switching circuit for enhancing amplitude comparison. A clocking system alternately actuating pairs of the integrators is also disclosed.

Practical considerations for analog operation of bucket-brigade circuits

Abstract: The bucket-brigade circuit offers a means of implementing a clock-controlled analog delay line in monolithic form. Operating in the sampled-data domain, it combines some of the advantages of both analog and digital circuits and appears to have a strong application potential in analog signal processing systems. In this paper, the analog operation of bucket-brigade circuits is described with respect to such practical operating considerations as bandwidth, dynamic range, linearity, power dissipation, baseband, signal recovery, a clock waveform noise. Experimental results from p-channel MOSFET and n-channel JFET brigades are presented.

Multiplexed digital data communication system

Abstract: A multiplexed digital data communication system wherein analog signals received from a conventional telephone system having a plurality of channels are multiplexed at a high sampling rate and converted to a series of discrete digital signals in a series of time slots. The system includes data transmission means for substituting data signals for said discrete digital signals in periodically spaced time slots. The communication system would include a plurality of local stations coupled to a common transmission line to which the series of discrete digital signals is applied, each of the local stations being adapted to demultiplex and convert to analog signals the portion of said discrete digital signal intended for it, and to supply said analog signals to the user. Similarly, the local station can multiplex and digitize user initiated analog signals for application to the transmission line, while the central station has demultiplexing and digital to analog capabilities.

Analog to digital converter of the parallel comparison

Abstract: An analog-to-digital converter for converting at a high rate an analog input signal into a digital signal by comparing it with a predetermined reference voltage parallelly. The converter comprises a plurality of parallel-connected comparators having window type comparison characteristics and each of which produces a binary-code signal of "1" or "0" only when the analog input signal is at a value within a window, that is, between a couple of reference voltages predetermined for respective comparators, and a code converter for converting the parallel output signals from the comparators into a series of binary-code signals having a predetermined number of bits.

Digital to analog converter

Abstract: An arrangement for converting digital signal to analog signals comprising a comparator, a comparison digit generator and an input digit generator. The ordered inputs and outputs of the comparator and the comparison digit generator, respectively, are connected in a predetermined permuted manner.

Automatic cable equalizer

Abstract: Disclosed is an active data transmission cable equalizer which minimizes regeneration errors by maximizing the ''''eye opening'''' of signals emanating out of digital signal transmission cables. Equalization is achieved by monitoring the equalizer''s peak output signal, by adjusting the gain k, of the equalizer, to maintain a constant output signal level, and by altering the frequency of a simple real zero, g, in the equalizer''s transfer response in accordance with the relation 1/k K1g + K2, where K1 and K2 are equalizer constants.

Pulse coded railway signal system

Abstract: A railway signalling system using coded digital signals impressed on the tracks for direct or computer directed block signal control, the presence of a train on a track section causing shunting of the signals and an indication from a receiver which operates in a fail-safe configuration in each signal circuit first and second tone oscillators provide carrier signals which are modulated in a specific digital pattern and applied to the tracks A tone sensitive receiver separately detects the carrier signals and provides pulse train outputs which are decoded in a binary counter and coincidence gate circuit for ascertainment that the correct digital code pattern has been received Signals are developed for energization of an oscillator, the output of the latter being amplified for direct or computer directed block signal control More than one signal circuit can be employed on common tracks for separate or overlapping signal control by the selection of different pairs of operating frequencies, readily accommodated by plug-in filter substitution

Auto bias control apparatus

Abstract: Auto bias control apparatus for controlling the potential applied to a development electrode of a development station includes a sensor for sensing the electrostatic field strength of longitudinal increments of a charged image area of a movable photoconductor upstream from the development station to produce an analog signal representative thereof. The apparatus further includes an analog to digital converter adapted to convert the analog signals to a digital signal, and a digital storage device such as a digital computer for storing such digital signals and at a selected time cause appropriate digital signals to be applied to a digital-to-analog converter wherein it is reconverted to an analog form and applied to the development electrode just as its corresponding movement of the image area enters the development station.

Method and system for testing signal transmission paths

Abstract: The disclosure relates to a method and system for testing a plurality of paths over which discrete d.c. signal levels are transmitted between a digital computer and external equipment. A particular configuration of discrete d.c. signal levels is applied to the input or output paths and a signal generated which is related to the sum of the d.c. signal levels on the paths to be tested. A test circuit in a computer input/output unit generates a reference signal and the sum signal may then be evaluated. An unfavorable evaluation may activate a fault indicator.

Signal distribution system

Abstract: A system for distributing and routing a large number of audio-video signal channels is described. The system includes an input multiplexer and signal distribution networks, a matrix of switch groups and an output demultiplexer. In the input multiplexer the audio signals accompanying each video signal in each channel are digitized and the resulting digital signal angularly modulated to produce signals modulated by the digital signals and translated to a frequency region above the region of the video. A composite signal including the video and the angularly modulated audio signals are applied to the input distribution networks to drive a matrix of switch groups. Each output of the matrix switch has as many selectable inputs as there are input channels. Outputs are organized in groups to facilitate input distribution. Inputs are organized in blocks to facilitate input selection. An output demultiplexer is provided for each output and reconstructs the video and audio signals which are routed thereto by the matrix switch.

Method and circuit for calculating the square root of the sum of two squares

Abstract: An arithmetic logic circuit for performing an algorithm which approximates the square root of the sum of two squares. A novel hardware arrangement and method are disclosed which employ EXCLUSIVE OR circuits instead of a conventional 2''s complement arrangement provided by conventional adder-subtractor circuits. The values to be squared are converted to positive value digital signals, compared, and the control signal from a comparison circuit used to command the full value of the larger digital signal and half the value of the smaller digital signal into an adder circuit which receives a correction signal in the event either of the input digital values is negative. The correction signal may be added to the least significant order of the adder output signal or to the next to least significant order depending upon whether the larger or smaller of the digital signals is negative.

Digital phase-locked loop

Abstract: An all digital phase-locked loop derives a loop output signal from an accumulator output terminal. A phase detecting exclusive OR gate is fed by the loop digital input and output signals. The output of the phase detector is a bi-level digital signal having a duty cycle indicative of the relative phase of the input and output signals. The accumulator is incremented at a first rate in response to a first output level of the phase detector and at a second rate in response to a second output level of the phase detector.

Dual slope type resistance deviation measuring apparatus

Abstract: A resistance deviation measuring device, of the type used for measuring a temperature with temperature-sensitive resistance and for obtaining a digital signal representing the measured temperature, is characterized by a simple and reliable arrangement operating with the characteristics of a dual slope type analog-digital converter, i.e., with an integrator for first integrating an unknown analog signal for a predetermined time period and for then integrating a reference signal of inverse polarity with respect to the analog signal until the integrator is restored to its initial value, and with digital counting means for digitally measuring a time interval ending when the integrating means is restored to its initial value. The resistance deviation measuring device of the present invention connects the unknown temperature-sensitive resistance to a reference resistance in series, and uses a series voltage source to generate the same current flow through both resistances to produce the unknown analog signal and reference signal respectively. A switch connects the unknown resistance to the integrator for the predetermined time period, and then connects the reference resistance to the integrator until it is restored to its initial value. A timing circuit initiates the counting of the time interval measured by the digital counting means a predetermined amout of time, equal to the predetermined time period, after the reference signal is connected to the integrator. The digital counting means then digitally represents the deviation of the unknown resistance from the reference resistance.

Digital phase measuring system

Abstract: A system for measuring the phase difference between two signals and having a digital readout. Each of the two signals are fed to Schmitt trigger circuits which convert the sine wave signals to square waves. The two square waves are compared for coincidence in a discriminator, the output thereof being converted by a logic circuit to a form for displaying the digital phase difference of the two signals.

Digital data compression method and system

Abstract: A data compression method and system for logarithmically compressing a digital data signal is disclosed. A digital signal related to the number of successive binary bits of one signal level in the digital data signal is generated by counting the number of successive bits of the one level in the order of decreasing significance of the bits of the digital data signal. The digital signal is then combined with a predetermined number of the uncounted bits of the digital data signal to provide a compressed data signal having fewer bits than the original digital data signal. The digital signal is preferably generated by entering the digital data signal into a serial shift register and monitoring the stage of the shift register initially containing the most significant bit. The digital data signal is then shifted through the shift register in a direction tending to shift each bit into the monitored stage and the number of shifts is counted by a binary counter. The counter is inhibited when a predetermined binary level is detected in the monitored stage of the shift register and the count in the counter is combined with a predetermined number of the bits remaining in the shift register to form the compressed data signal.

Digital indicator for cameras

Abstract: This invention relates to a digital indicator for cameras comprising a light measuring circuit for producing a voltage of the sum of an analog voltage obtained by measuring the object brightness and an analog voltage corresponding to at least the film speed, a circuit for converting the analog voltage derived from the light measuring circuit into a digital signal for providing an indication of an exposure condition, and an indicator unit having a main indicator unit including luminous elements each supplied with the digital signal from the converting circuit to be energized to indicate the corresponding exposure condition and a subindicator unit including luminous elements, each indicating an exposure condition corresponding to a value between adjacent stages of the exposure condition indicated by the main indicator unit.

Electronic fabric length measuring and cost calculating system

Abstract: An electronic system for rapidly and accurately measuring and displaying fabric length and for calculating and displaying the total cost of the measured fabric as the desired length of fabric is removed from a roll or bolt for retail sale thereof. The fabric is drawn over a measuring roller in engagement therewith and a digital signal related to fabric length is generated and displayed. The fabric length signal is multiplied by price per unit length and the resultant cost of the measured fabric may also be displayed. The system includes provision for resetting the electronic circuitry at the beginning of each measurement and for preventing movement of the measuring roller between measurements.

Signal processor and subassemblies therefor

Abstract: A signal processor suitable for real time processing of a complex signal having a relatively narrow frequency spectrum is disclosed. Such signal processor includes a so-called delay line time compressor adapted to receive digital signals corresponding to samples of the complex signal into selected stages thereof and to convert such digital signals into a resulting complex signal, analogous to the complex signal being processed, but having a relatively wide frequency spectrum. The signal processor also includes a digitally controlled oscillator in combination with a single side band generator to produce frequency-varying heterodyning signals which, when mixed with the resulting complex signal, permit separation of the frequency components of such resulting signal to permit any further separate processing of each one of such components.

Method and apparatus for synchronizing modular seismic system

Abstract: A method and apparatus for synchronizing a modular seismic system wherein each seismic station includes a data acquisition module having means for sampling the geophone signal, a gain ranging amplifier adjusting the gain of the signal amplifier and an analog to digital converter converting the amplified signal to digital form The module also includes means for transmitting to succeeding stations digital signals received from previous stations and its own digital signal All of the modules are coupled in series by coaxial cables while power is supplied over a separate two-conductor power cable A coded word is transmitted over the power cable to synchronize the sampling of the geophone signal and control operation of the module