Showing papers on "Effective number of bits published in 1994"

Data block format for software carrier and player therefor

Abstract: A system using an optical disk format for representing several synchronized signals, e.g. multiple versions of motion pictures and multiple soundtracks which is made up of an optical disk (23), signal processors (67, 71), buffer circuitry (53, 55, 57, 59) and audio (91) and video (94) output devices. All signals are represented digitally, and the bits are arranged in data blocks. Each data block may contain a variable number of bits for each signal, ranging from none to many (relative to the other signals). This allows each signal to be represented by a variable rate bit stream, without one signal necessarily constraining another as far as bit representation is concerned. Multiple buffers are provided to insure that there are a sufficient number of bits available for each signal as required for immediate needs. When any buffer is full, reading of the data blocks stops temporarily so that no bits are lost.

Method and apparatus for coding digital sound by subtracting adaptive dither and inserting buried channel bits and an apparatus for decoding such encoding digital sound

Abstract: For encoding sound received as a stream of multibit input sample, from a finite length sequence of input samples, an instantaneous audibility threshold characteristic is determined. Next, a shaped, dither determined, signal is subtracted from the input samples to produce processing samples. Subtracting a dither signal dynamically ignores processing sample bits below the threshold. Next, quantization by a variable number of bits below the threshold is performed, while retaining all sample bits above the threshold. The ignored bits are replaced by the dither signal as buried channel bits at an adjustable number of bits per sample. Therefore, upgraded samples have non-ignored bits and buried channel bits are obtained and outputted. The noise is shaped through shape-filtering a difference between the upgraded samples and the processing samples, which shape-filtering may amend a received white-noise-like signal towards an actual threshold-versus-frequency characteristic.

Approaches and analysis for on-focal-plane analog-to-digital conversion

Abstract: This paper presents approaches for on-focal-plane analog-to-digital conversion (ADC). Common approaches and architectures for ADC and their utility for on-focal-plane integration are discussed. Candidate approaches are analyzed with respect to required amplifier gain, bandwidth, capacitance matching, noise and offsets as a function of ADC resolution. A column-parallel ADC architecture appears to be an effective compromise of chip area, power, circuit speed and ADC resolution. The discussion is valid for both infrared focal-plane arrays and visible image sensors.© (1994) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

High performance error control coding in channel encoders and decoders

Abstract: An improved error control coding scheme is implemented in low bit rate coders in order to improve their performance in the presence of transmission errors typical of the digital cellular channel. The error control coding scheme exploits the nonlinear block codes (NBCs) for purposes of tailoring those codes to a fading channel in order to provide superior error protection to the compressed half rate speech data. For a half rate speech codec assumed to have a frame size of 40 ms, the speech encoder puts out a fixed number of bits per 40 ms. These bits are divided into three distinct classes, referred to as Class 1, Class 2 and Class 3 bits. A subset of the Class 1 bits are further protected by a CRC for error detection purposes. The Class 1 bits and the CRC bits are encoded by a rate ½ Nordstrom Robinson code with codeword length of 16. The Class 2 bits are encoded by a punctured version of the Nordstrom Robinson code. It has an effective rate of 8/14 with a codeword length 14. The Class 3 bits are left unprotected. The coded Class 1 plus CRC bits, coded Class 2 bits, and the Class 3 bits are mixed in an interleaving array of size 16x17 and interleaved over two slots in a manner that optimally divides each codeword between the two slots. At the receiver the coded Class 1 plus CRC bits, coded Class 2 bits, and Class 3 bits are extracted after de-interleaving. Maximum likelihood techniques using soft decision are employed to decode the Class 1 plus CRC bits as well as the Class 2 bits. The CRC is also used to further reduce the bit error rate (BER) of the subset of Class 1 bits over which it was applied by using generalized decoding techniques. In addition to the CRC based bad frame indication flag, raw channel bit error rate estimates for each codeword are also sent to the decoder as well.

Compressed data recording and/or reproducing apparatus and signal processing method

Abstract: Apparatus for recording an information signal as bit-compressed digital data. The apparatus comprises a bit compressor and a recording system. The bit compressor receives the information signal as digital data. The digital data include bits, and the bits include redundant bits. The bit compressor compresses the digital data by removing only the redundant bits from the digital data to generate the bit-compressed digital data at a variable bit rate. The redundant bits are bits that result in a quantizing noise level lower than an allowed noise level at which the quantizing noise is imperceptible to a human auditory sense. The allowable noise level is determined by a masking threshold and a minimum audibility limit. The recording system receives the bit-compressed digital data from the bit compressor and records the bit-compressed data on a recording medium.

Method and apparatus for micropower analog-to-digital conversion in an implantable medical device

Abstract: A micropower analog-to-digital converter (ADC) for use in an implantable medical device is disclosed. The ADC achieves a high conversion speed at micropower levels through a number of timing and circuit improvements over the conventional implementation of the successive approximation ADC architecture. The ADC includes a digital-to-analog converter (DAC) that preferably is implemented as a binary-weighted, switched capacitor array that employs top plate charging and performs bipolar conversion. The DAC provides an analog output signal representing array charge to a comparator. During a comparator latch phase, the DAC asynchronously determines a bit of the ADC digital output signal in response to the comparator output, and initiates a test of the next least significant bit during the same latch phase. Further, the DAC analog output signal is timed to settle during the latch phase in response to both the bit update and the next bit test. In conjunction with increasing conversion speed, the DAC reduces power requirements by using a power gated buffer that selectively increases the power of the ADC input signal only when necessary to drive the ADC conversion circuitry. Further, the comparator includes a precharged static memory cell to avoid crossover currents. Finally, the ADC includes a digital offset correction DAC that corrects not only the cumulative offset voltage generated by components of the ADC, but also the offset voltage of any device that provides the ADC input.

A 5 V, 6-b, 80 Ms/s BiCMOS flash ADC

Abstract: A 5 V single supply, 6-bit flash A/D converter (ADC) has been developed that supports sampling rates of up to 80 Ms/s. The converter is optimized to operate in undersampling applications where the ADC has to deliver greater than 5.2 Effective Number Of Bits (ENOB's) with input frequencies well beyond Nyquist. Excellent dynamic linearity performance has been achieved with input frequencies up to 75 MHz and a gain flatness of better than 0.1 dB is obtained over the input signal spectrum of 50 MHz-95 MHz. This ADC is fabricated on a 1.0 /spl mu/m advanced BiCMOS process that features trench-isolated bipolar devices with an f/sub t/ of 10 GHz. >

Booth array multiplying circuit having carry correction

Abstract: A multiplying circuit having sign carry correcting circuits which set all bits of a multiplier Y subjected to sign extension to a certain specific value ("0" or "1"), and when a sign bit, which is the highest bit of effective data in the data to be multiplied, is carried, a specific value signal is input to a bit input portion of a Booth decoder, receiving both the least significant invalid bit and the most significant effective bit of the multiplier, according to a value of a sign extension control signal. In addition, a value inputted to partial product adding circuits from an intermediate result shift circuit is set to a multiplicand value according to the value of a predetermined number of least significant bits of the multiplier, and the multiplier bits excluding the predetermined number of least significant bits inputted to the intermediate result shift circuit are inputted to multiple generating circuits. Thus, a sign extension function or the number of adding circuits to be added in the case of producing a remainder in the number of partial products, at the time of dividing the multiplication into a plurality of operation cycles, are reduced to suppress a circuit scale from becoming larger.

Apparatus and method for a pseudo-random number generator for high precision numbers

Abstract: The present invention pseudo-random number generator produces a high precision number suitable for use as a data encryption communications security (COMSEC) key from a highly mobile computer platform. The random number generator is especially suitable for use with military radios and other like applications requiring a random number bit string of high precision. The present invention random number generator produces four pseudo-random numbers of 32-bits and uses only the last 28 bits of each number. A multiplicative linear congruential generator with multiplier 16807 and prime modulus 2 31 -1 is used to produce the 32-bit pseudo-random numbers. This generator produces a sequence of remainders of large modulus. The last 28 bits of the 32-bit numbers are combined to produce one high precision number of 112 bits. The first 28-bit number would be shifted left 84 bits, the second 28-bit number would be shifted left 56 bits, the third 28-bit number would be shifted left 28 bits and the last 28-bit number would not be shifted. The three shifted results would be logically ORed together to produce the 112-bit pseudo-random number. The high precision number preserves the statistical nature of the low precision pseudo-random numbers.

Method and structure for reducing carry delay for a programmable carry chain

Abstract: A carry-lookahead structure for programmable architectures includes a number of M-bit carry lookahead units, each M-bit unit having two parallel programmable carry paths having AND gates controlled by configuration bits to program the beginning and end of an operating carry chain within the M-bit units, as well as the beginning locations in each unit, one path generating a first set of carry bits for the case of the carry-in equal to 0, and the other generating a second set of carry bits for the case of the carry-in equal to 1, and at least one multiplexer controlled by the carry-in for selecting one of the two carries at the most significant bit of the first and second sets of carry bits as carry-out of the unit. Each M-bit unit may further include multiplexers controlled by the carry-in for selecting which of the first and second sets of carry bits are the correct carry bits for addition and M sum logic elements for generating the outputs of sum bits. An alternative is an adder in which the precomputation of the sums is performed for the two possible values of carry-in in each M-bit unit, providing two sets of sum bits, and where multiplexers select which of the two sets of the sum bits is the correct sum and which of the two carry bits produced in the most significant bit of the unit is used as the carry-out of the unit in response to the actual carry-in value of the unit.

Arithmetic apparatus for digital signal processor

Abstract: In a digital signal processor, an arithmetic apparatus capable of performing Viterbi decoding processing at a high speed with minimum addition of hardware and least overhead of memory. Pathmetric value and branchmetric value read out from first and second memories on two paths are simultaneously added by an adder at most significant bits and least significant bits thereof. A comparator compares values of the most significant bits and the least significant bits output from the adder to generate a path select signal indicating the value which is pathmetrically smaller. The select signal is stored in a shift register on a bit-by-bit basis. Of the values of the most significant bits and the least significant bits of a register storing the output of the adder, the smaller one as decided by the path select signal is written in the memory at eight most significant bits or least significant bits thereof via distributor, a bus and a register.

A-D converter testing circuit and D-A converter testing circuit

Abstract: There is disclosed an A-D converter testing circuit wherein exclusive-OR gates (13a, 13b) provide the exclusive-OR of the high-order bits (D 1a , D 1b ) of the outputs of A-D converters (12a, 12b) and the exclusive-OR of the high-order bits (D 1b , D 1c ) of the outputs of A-D converters (12b, 12c), respectively, and an OR gate (13c) provides the logical sum of the outputs of the both gates, which is "L" if all of the bits (D 1a , D 1b , D 1c ) are equal. A tri-state buffer (15a) receives the output of the OR gate (13c) at its control end and receives the bit (D 1c ) at its input. When all of the A-D converters are normal, all of the bits (D 1a , D 1b , D 1c ) are equal and are applied to the output of the tri-state buffer (15a). When one or some of the A-D converters are abnormal, the output of the tri-state buffer (15a) enters a high-impedance state. The A-D converter testing circuit, therefore, rapidly judges whether the A-D converters are defective or non-defective.

Effects of quantization noise in parallel arrays of analog-to-digital converters

Abstract: High-speed A/D conversion can be achieved by using a parallel array of digitizers interleaved in time and in voltage Alternatively, the input analog signal can be first decomposed into several frequency bands and then have each frequency band digitized by a separate A/D converter This paper investigates the quantization noise effects in such structures, and shows that by using a filter bank before and after a parallel array of A/D converters, an increase in the effective number of bits of resolution can be obtained >

Frame transmission system

Abstract: In a frame transmission system for transmitting multi-frames of a DS3.C-bit parity frame system as prescribed in American National Standard and also in Proposed Contribution to CCITT (ITU-T), C1-bits assigned to the prior art DS3.C-bit parity frame, i.e., 3×3=9 C-bits (fixed bits) for the 2nd, 6th and 7th channels, are used as control bits of DS2 level signal for intrinsic purposes. These bits may be processed in their entirely in the same manner as with the prior art control bits.

Start code for signalling bits

Abstract: In an extended television signal comprising signalling bits for conveying control information to control an extended decoder, the signalling bits comprise a start code and data bits, the start code's main lobe of spectral energy resides in the lower spectral area of a baseband television signal below 2 MHz and preferably below 1.7 MHz, the start code is preferably (almost) DC-free, and the start code has good aperiodic correlation properties and a predetermined minimum bit Hamming distance to the data bits when shifted in the direction of the data bits following the start code.

Cyclic redundancy check synchronizer

Abstract: A cyclic redundancy check synchronizer includes an N-byte shift register for shifting an input byte string by N bytes and N-1 bytes, a compensation polynomial driver for driving a compensation polynomial by modulo-2-dividing bits of a byte output from the Nth stage of the N-byte shift register by a generator polynomial and shifting the resultant remainder by one bit in a direction toward higher-order bits, and a calculator for inputting bits of an output byte from a remainder register as high-order bits and bits of an input data byte as low-order bits and for performing compensation polynomial modulo-2 subtraction and generator polynomial modulo-2 division for the inputted bits. The cyclic redundancy check synchronizer also includes a block synchronization identifier for searching for syndrome output signals from the calculator at an interval of a byte time to check whether the same syndrome signal is outputted from the calculator successively a predetermined number of times or more at an interval of a block period, and a data selector for selecting bits constituting a byte from among output bits from the N-byte shift register according to a certain one of the syndrome output signals from the calculator resulting in a block synchronous state in response to a data selection signal from the block synchronization identifier to output byte-synchronized data.

Digital signal decoding processing unit

Abstract: PURPOSE: To simplify the circuit configuration and to reduce the effect of error onto waveform equalization by limiting the number of state nodes being objects of arithmetic operation to be a prescribed number or below at all times. CONSTITUTION: A maximum likelihood path prediction circuit 15 uses an equalization value in several bits consecutive to discrimination object bits and selects a shortest path from each node with respect to the several bits. Furthermore, a metric calculation circuit 16 calculates all metric values with respect to object bits. A maximum likelihood candidate selection circuit 17 calculates a metric of a shortest path from a survival node in bits of decoding objects up to several bits before. A path decision circuit 21 compares metric values fed from the maximum likelihood candidate selection circuit 17 to decide a survival node at a succeeding time. Furthermore, a path metric update circuit 19 calculates a metric difference between survival nodes and provides the result of calculation to the maximum likelihood path candidate selection circuit 17. Then a path memory circuit 18 converges a path selected by the path decision circuit 21. The converged decoding result is outputted as a final decoding result. COPYRIGHT: (C)1996,JPO

Motion estimation with bit rate criterion

Abstract: A new motion estimation technique is described herein which directly detects the number of bits required to be transmitted to convey the difference between the predicted video data and the current video data, where a fewer number of bits used to convey the difference corresponds to better motion estimation. The search criterion for the best estimate of movement of a block is the minimum number of bits for conveying this difference instead of minimizing the mean squared error (MSE) or mean average difference (MAD). Thus, complex calculations involving MSD or MAD are avoided. The motion estimator of the preferred embodiment uses a look-up table to convert motion compensated difference signals for a block of pels into the number of bits required to be transmitted to convey the difference signals. When it has been determined that a certain estimated displacement of a block would require the fewest number of bits to be transmitted, that displacement is selected as the best estimate, and the corresponding motion vector is transmitted along with a motion compensated difference signal containing the fewest number of bits.

Analog-to-digital converters with dither signal

Abstract: An improved sigma-delta analog-to-digital converter (ADC) is disclosed herein. The digital converter includes a dither circuit fabricated within the package of the ADC. The circuit is configured to apply a dither current to the analog input of the ADC. The frequency of the dither current is selected based upon the bandwidth of the analog signals for which the ADC is designed to sample and convert to digital signals. Application of the dither current to the input of the ADC reduces quantization noises produced as a result of certain ranges of DC offset voltages found within analog signals applied to the ADC.

Apparatus for quantizing pixel information to an output video display space

Abstract: A quantization processor (64) is provided that is operable to provide an error diffusion for adjacent output pixels in an output display space. Three quantization processors (300), (302) and (304) are provided for the three colors of the video RGB format. A full adder (312) is provided for receiving both an error signal and an input pixel value. The composite output is input to an input/output error register 328 that is operable to store bits of the output of the adder, determined to be output bits, and also to store the remainder of the bits that are determined to be error or truncated bits. The error or truncated bits are fed back to the input of the full adder. A rounding decoder (306) is operable to receiving a masking word, such that the outputs from the register (326) are either selected as bits to be truncated, provide an error to be added to the next sequential pixel value, or they are selected as outputs. The register (326) is operable to store the error bits for the next sequential cycle.

Half-band filter and method

Abstract: A digital half-band filter with mutliplications using Wallace trees which have lower bits truncated for reduction in size and with a true/complementer providing saturation compensation together with accumulator overflow compensation by monitoring bits more significant than the output bits.

Combined conventional/neural network analog to digital converter

Abstract: An analog-to-digital converter employs both flash and neural converters for converting an analog input voltage. The flash converter converts the higher-order bits in a single clock cycle. Values of the lower-order bits are determined by outputs from comparators with reference voltages provided by digital-to-analog converters. The D/A converters receive inputs from the flash converter as well as from those comparators which provide output results for higher-order bits. This interconnection of D/A converters and comparators thus forms a neural network for determining the value of the lower-order bits.

Comparative ADC performance evaluation using a new emulation model for flash ADC architectures

Abstract: This paper investigates various flash A/D converters (ADC's) using a new emulation model which mimics the gate-level architecture of a flash ADC with any number of bits, n. The model is used for studying the effects of noise and offset voltages at the comparator inputs on the ADC output deviation using a mean-square error criterion. The first ADC investigated is the full-flash one, which is compared with the successive-approximation ADC for the same n. Then, two-step flash ADC's (i.e. half-flash) are investigated, with and without an interstage gain. Finally, error correction is attempted in conjunction with the later half-flash type.

Apparatus for converting two dimensional pixel image into one-dimensional pixel array

Abstract: An converter apparatus to convert the (X, Y) coordinate of the two-dimensional screen position of a pixel to a linear address. The converter apparatus, which can be used with a variety of video displays of various resolutions including 1280×1024, 1152×900, 640×480, 1024×768, 1600×1280, and 800×600, contains three circuits in parallel disposition to receive and process various portions of the X and Y bits, and to output a Z-bit linear address. The first circuit mainly contains a multiplexer and it receives lower X bits as inputs; the second circuit contains a plurality of adders and multiplexers and a logical operation circuit, and it receives higher X bits and lower Y bits as inputs; and the third circuit mainly contains a multiplexer and it receives higher Y bits and at least a portion of the lower Y bits as inputs. The converter apparatus does not require a system CPU thus very high speed conversion can be achieved.

A 13-Bit 10-Mhz Adc Background-Calibrated with Real-Time Oversampling Calibrator

Abstract: A real-time digital-domain code-error calibration technique is developed and demonstrated in this fully-Merential5-volt 13-bit IO-= BiCMOS ADC. The calibration process does not interfere with the normal operation of the converter but improves its linearity in real time while the converter is working. The core of this technique is an oversampling sigma-delta ratio calibrator working synchronously with the converter in background.' 1. Introdiictiou Existing self-calibration techniques for data converters interrupt normal conversion cycle for calibration[ I]. Temperature variation, device parameter drift, etc., may cause the calibration data to become invalid unless the converter is periodically re-calibrated. Other analogdomain calibration techniques are limited by the analog signal accuracy and circuit noise[2]. A novel digital-domain, code-error background calibration technique is implemented in this experimental 13-bit 10-MHZ ADC. The calibration procedure is virtually trans arent to the normal converter operation, thus allowing tg e converter to operate continuously even while being calibrated. 2.Real-Time Digital Calibration Technique In a multi-stage type ADC, the linearity of the D-to-A converter @AC) in the first stage determines the overall transfer characteristics of the ADC. To calibrate the ADC it is necessary to correct the linearity error of the fist stage DAC. In this ADC, a resistor-string DAC is used in the first stage because it allows both the calibrator circuit and the ADC amplifier to tap different DAC outputs simultaneously without affecting each other, provided that the DAC outputs settle within the clock phase. The DAC output errors are digitized by the calibrator and later subtracted from the raw output codes with the code-error calibration technique[3], To measure the resistor DAC error, a ratio-measurement method has been used. A switched-capacitor subtracter is used to measure the mid-point voltage error of a given section of the resistor string. A simplified diagram is shown in Figxe 1. Assuming ideal conditions,C, = C2 = C,,

Method of preparing data, in particular encoded voice signal parameters

Abstract: Method of preparing data, in particular voice signal parameters for transmission at a low bit rate, identical signal parameters are combined interval by interval in quantized form; for further bit reduction, bits are suppressed from the total number of bits of at least two intervals, the bit difference to be suppressed being formed on the basis of the total number of unreduced bits with respect to the next-higher power of two; and the procedure supplies a better voice quality than in the case of changing the number of quantization stages by multiples of 2.

BICMOS cache TAG having ECL reduction circuit with CMOS output

Abstract: A cache TAG RAM (25) includes a reduction circuit (39) for comparing match signals from a plurality of exclusive OR logic circuits (33, 34) and provides a hit signal when all of the TAG address bits of a stored TAG address is the same as input address bits. The reduction circuit (39) provides a miss signal when any one or more of the bits of the stored TAG address is not the same as the corresponding bits of the input address bits. In one embodiment, the reduction circuit (39) uses a plurality of transistors (77, 78) coupled to a conductor (75) for discharging the conductor (75) if one of the exclusive OR logic circuits (33, 34) indicates a miss. In another embodiment, the reduction circuit (39") charges the conductor. The comparison can be made using signals having small signal swing at high speed, and a reference voltage is not needed for the comparison.

Recent results from tests of fast analog-to-digital converters

Abstract: We present results from tests of eight, ten, and twelve bit ADCs that operate in the range of 10 to 120 megasamples per second. We use a test bench and software we have developed to perform the tests on as wide a range of devices as possible. By testing devices with the same input signals, the same software, and the same parameter definitions, we make possible direct comparisons between competing devices. Important parameters measured include integral and differential nonlinearity, effective number of bits, and word error rate. While the tests are intended primarily to benefit the design of high rate physics experiments, the results are also useful to workers in other fields. >

High speed analog-to-digital converter using cells with back-to-back capacitors for both rough and fine approximation

Abstract: A high conversion speed analog-to-digital converter is constituted by a plurality of comparison cells which in successive steps determine first the four most significant bits of the analog-to-digital conversion and then the least significant bits of the same, having first accomplished the reconversion of the four most significant bits to analog and their subsequent subtraction from the input signal.

Method of recovering lost bits in a digital transmission

Abstract: The invention relates to a method of recovering lost bits in digital transmission. The invention can be applied in ATM networks or networks in which the receiver utilizes soft decoding. A number of data bits dl-dn are transmitted together with a number of control bits cl-ck. The control bits are calculated in the transmitter using a number of parity constants pll-pkn such that a corresponding number of parity relations are fulfilled. In the receiver, the positions of the lost data bits are detected and a number of syndrome bits sl-sk are calculated from the transmitted data bits and control bits. Then the lost data bits can be recovered by mapping syndrome bits indicating the values of the lost data bits. By using the knowledge about the positions of the lost data bits a reduced number of control bits are required compared with the prior art.