Showing papers on "Electronic packaging published in 2023"

Board-Level Drop Impact Reliability Analysis of Dual-Side Molding System-in- Package (SiP) Modules

Abstract: System-in-package (SiP) modules are widely used in portable electronics such as Internet of Things (IoT) devices and mobile consumer equipment since they integrate multiple components in a single package and thus facilitate device miniaturization. An advanced packaging technology referred to as dual-side molding (DSM) has recently been proposed as a means of achieving even smaller form factors and lower cost solutions. However, shrinking the package size reduces the solder joint connection area between the SiP module and the printed circuit board (PCB). Consequently, the board-level drop reliability may be severely impaired. Accordingly, the present study utilizes a numerical model to investigate the board-level solder joint reliability of a DSM SiP package in drop impact tests performed in accordance with the Joint Electron Device Engineering Council (JEDEC) standard. The validity of the numerical model combined with a full-factorial design method is then employed to examine the effects of the main design parameters of the DSM SiP package on the reliability of the solder joints in the drop impact test. Overall, the present results show that a higher EMC coverage of the solder ball joints yields a significant improvement in the solder joint reliability. In addition, a larger solder joint volume is beneficial in reducing the solder joint stress by absorbing a greater proportion of the impact load and energy produced in the drop impact event.

The preparation of silicon carbide and its corresponding properties for electronic packaging applications

Abstract: Traditional packaging materials are suffering from poor high-temperature-using, however, the SiC own ideal coefficient of thermal expansion (CTE) and thermal conductivity (TC), and at the same time, it can be used in high temperatures meeting the requirement of the advanced electronic packaging. But traditionally, SiC is made at a high temperature and with a complex producing process. Some researchers are focused on SiC with some Al additions, but we know that Al will volatilize when the samples are heated over than melt-point, so this method would also strict its applications. Other works had been taken on diamond addition to realize packaging function, but this method needed a high-temperature infiltration process too. In fact, the non-method above was economic or convenient to manufacture in nowadays industry practice. Fortunately, a new way to gain dense SiC at a very low temperature in an open environment had been gotten by our group.

Impact of Viscoelastic Properties on Package Warpage Prediction

Abstract: Warpage is a critical issue concerning electronic plastic packages and is mainly related to the epoxy molding compound (EMC). The molding process requires a large change in temperature, creating thermal gradients and mismatches which can lead to thermal stresses generating package deformation. Problems in controlling warpage will result in assembly yield loss and later in reliability issues, such as delamination and solder joint failures.Therefore, a solution to improve the reliability of packages is the prediction of warpage by employing finite element analysis (FEA). However, the standard FEA treats only linear elastic material properties lacking on the consideration of EMC viscoelasticity. With the aid of moldflow simulation tool, this work gives a comprehensive assessment to anticipate package warpage behavior with a validated model which considers the viscous and elastic properties of EMC by applying the Generalized Maxwell Model. The study is supported by experimental analysis as well as numerical modelling.

Electronic Packaging Interfacial Strength Measurement and Delamination Investigation

Abstract: The microelectronics package is not only interconnecting the electronic signals from die to the printed circuit board (PCB), but also avoid the chips fracture during the manufacturing process or subsequent reliability testing stage. In general, the epoxy molding compound (EMC) are widely used in electronic packaging since its better processing capability and the lower circuit signal delay. However, the interfacial delamination in encapsulated silicon devices is a concern problem, especially for the interfaces between the copper lead-frame (LF) pads and EMC due to the weaker adhesion strength. To investigate the fracture of the copper leadframe/EMC interface of the Very Very-thin Quad Flat No-lead (WQFN) package, the double cantilever beam (DCB) experimental testing and numerical model based on the virtual crack closure technique methodology were constructed. Finally, a 2 ⁴ full factorial design with the analysis of variance (ANOVA) method is then employed to examine the effects of the main design parameters of the WQFN package (i.e., thickness of the epoxy molding compound (EMC), Die thickness, die bonding thickness, and die bonding size) on the strain energy release rate (SERR) between the copper and EMC under typical manufacturing thermal loading conditions.

Electronic Packaging Enhancement Engineered by Reducing the Bonding Temperature via Modified Cure Cycles

Abstract: Semiconductor packaging continues to reduce in thickness following the overall thinning of electronic devices such as smartphones and tablets. As the package becomes thinner, the warpage of the semiconductor package becomes more important due to the reduced bending stiffness and driven by thermal residual stresses and thermal expansion mismatch during the epoxy molding compound (EMC) curing to create the package. To address this packaging reliability issue, in this study, we developed a modified cure cycle that adds a rapid cooling step to the conventional cure cycle (CCC) to enhance the reliability of the EMC molded to a copper substrate (EMC/Cu bi-layer package) by lowering the bonding temperature of the EMC/Cu bi-layer package. Modeling of the package via Timoshenko theory including effective cure shrinkage allowed the rapid cooling step to be quantified and confirmed via experiments. The modified cure cycle resulted in a 26% reduction in residual strain, a 27% reduction in curvature, and a 40% increase in peel strength compared to the CCC, suggesting that this is an effective new method for managing warping effects in such packaged structures.

Board Level Reliability of Flipchip Package

Abstract: In the world of electronic materials, solder is a critical material that plays an important role in the first level (silicon to package substrate) and second level (package to printed circuit board) interconnection. As a joining material in electronic assemblies, solder provides electrical and mechanical connections. The increasing need for reliable electronic devices for harsh environment triggers the need for reliable solder joints. This study focuses on reliability of second level interconnections between package and printed circuit boards. Board level temperature cycling and mechanical drop performance of a 15 mm x 15 mm FCBGA test vehicle were evaluated with different package construction (lidded vs non-lidded), and BGA solder alloys (SA1, SA2, and SA3). Daisy chain packages were assembled on 1.0 mm thick PCB. Mounted units were thermally cycled between from -40C to 125C. Additional samples were evaluated in mechanical drop test conditions following JEDEC standards. Results showed that packages with SA2, and SA3 BGA had significantly higher board-level thermal cycling life compared to SA1. The best drop performance was achieved with SA1 solder. The performance trend among different solder alloys was found to be similar between lidded vs non lidded package. However, lidded package showed improved board-level reliability performance compared to a non-lidded package.

3D Printable, Form stable, Flexible Phase-Change-based Electronic Packaging Materials for Thermal Management

Abstract: Phase change materials (PCMs) have been proven to be promising electronic packaging materials to passively control electronics heating and cooling, but the poor thermal stability and processability greatly hinder their applications. Herein, flexible composite PCMs with perfect shape-stabilized, high latent heat energy storage density and good 3D printability were prepared using a scalable swelling strategy by limiting paraffin to a three-dimensional flexible polymer network. We successfully and accurately packaged the phase-change-based electronic packaging materials into the microelectronic devices according to complex circuits structure using fused jet deposition 3D printing technology. Compared with conventional electronic packaging materials, after packing our novel phase-change-based electronic packaging materials, the cooling effect of 13 ℃ can be achieved. This 3D printable shape-stabilized phase-change-based electronic packaging materials show promising thermal management ability and can effectively address the heat dissipation problem of integrated electronics.

Improvement in the Thermal Conductivity of Silver Epoxy Adhesive by Treating with Water Vapor

Abstract: With the miniaturization of electronic devices, electronic packaging has become increasingly precise and complex, which presents a significant challenge in terms of heat dissipation. Electrically conductive adhesives (ECAs), particularly silver epoxy adhesives, have emerged as a new type of electronic packaging material, thanks to their high conductivity and stable contact resistance. However, while there has been extensive research on silver epoxy adhesives, little attention has been paid to improving their thermal conductivity, which is a critical requirement in the ECA industry. In this paper, we propose a straightforward method for treating silver epoxy adhesive with water vapor, resulting in a remarkable improvement in thermal conductivity to 9.1 W/(m·K), three times higher than the sample cured using traditional methods (2.7 W/(m·K)). Through research and analysis, the study demonstrates that the introduction of H2O into the gaps and holes of the silver epoxy adhesive increases the path of electron conduction, thereby improving thermal conductivity. Furthermore, this method has the potential to significantly improve the performance of packaging materials and meet the needs of high-performance ECAs.

Packaging Induced Stresses in Embedded and Molded GaN Power Electronics Components

Abstract: Residual stresses created during the packaging process can adversely affect the reliability of electronics components. We used incremental hole-drilling method, following the ASTM E 837-20 standard, to measure packaging induced residual stresses in discrete packages of power electronics components. For this purpose, we bonded a strain gauge on the surface of a Gallium Nitride (GaN) power component, drilled a hole through the thickness of the component in several incremental steps, recorded the relaxed strain data on the sample surface using the strain gauge, and finally calculated the residual stresses from the measured strain data. The recorded strains and the residual stresses are related by the compliance coefficients. For the hole drilling method in the isotropic materials, the compliance coefficients are calculated from the analytical solutions, and available in the ASTM standard. But for the orthotropic multilayered components typically found in microelectronics assemblies, numerical solutions are necessary. We developed a subroutine in ANSYS APDL to calculate the compliance coefficients of the hole drilling test in the molded and embedded power electronics components. This can extend the capability of the hole drilling method to determine residual stresses in more complex layered structures found in electronics.

<scp>LED</scp> Packaging Manufacturing Technology

Abstract: LED packaging technology is central to the LED manufacturing industry. For stable and consistent quality, an in-depth knowledge of LED package manufacturing technology is essential. This chapter details the LED package manufacturing technology. One of the elements of LED packaging technology is the manufacturing process. Generally, all LED packaging processes begin with a die-attach process. Wire bonding is one of the main processes for creating electrical interconnection between die and substrate. Surveillance checking is one of the keys to process control as a line of defense in the LED manufacturing process. The encapsulation process is one of the most important processes in the LED packaging technology. There are many types of LED defects in the LED packaging industry. The chapter discusses some of the common defects and their impact on the electro-optical properties of LEDs.

High-Reliability Lead-Free Solders for Automotive Electronics

Abstract: Requirements for high-reliability lead-free solder alloys in automotive electronics are becoming more challenging as assembly designs require increased powder densities and miniaturization in combination with harsh operating conditions. Thermal cycling performance has been the primary factor for deciding on the suitability of a solder alloy for such applications. Solder joint reliability under thermal and mechanical stresses depends on the solder, packages, PCB, and assembly, including global and local CTE mismatch.Automotive electronic assemblies for critical applications commonly require operational temperatures around 150oC, while soldering temperatures need to be as low as possible (<250oC). To resolve performance gaps in Sn-Ag-Cu solders for such applications, alloying additives can be used for: i) lowering the melting temperature, ii) improving creep properties, and iii) improving fatigue life. This is exemplified here by comparing a high reliability alloy, commonly known as “Innolot” and SAC305. This work reviews some of the aspects related to such board level accelerated reliability tests and discusses these experimental results in terms of alloy composition, microstructure, and mechanical properties.

Thermal Stresses in a Bi-Layer Assembly in Electronics Packaging

Abstract: Bi-material interfaces have practical applications in semiconductor packaged devices as a typical semiconductor package is a layered assembly consisting of various materials having different coefficients of thermal expansion (CTEs). CTE mismatch-induced thermal stresses during heating, cooling, or temperature cycling cause failures of semiconductor devices in manufacturing and operation conditions. It is well known that the laminates develop free-edge stresses that are major causes of interface delamination or cracking. Timoshenko first developed analytical solutions for axial stress and curvature radius using classical bending theory. However, stresses at the end of a bi-material interface are neglected. Suhir developed analytical solutions for peeling and shear stresses near the edges, but the stresses are considered bound with certain values. When bi-materials are both considered linear elastic, the peeling stress is singular at the free edges. In this paper, finite element analysis is performed to investigate the stress and deformation of a bi-layer strip assembly. The axial stress that acts in the longitudinal direction of the assembly can be accurately predicted by Timoshenko’s theory. The curvature of the assembly, or warpage using the terminology in electronics packaging, can also be predicted accurately using Timoshenko’s equation. However, the peeling stress at the free edge appears to be mesh-dependent, indicating an infinite stress value. Despite the free surface at the free edge, shear stress is also mesh-dependent. The fracture mechanics approach is often used to take singular behaviors into consideration for the extraction of meaningful fracture parameters. However, only the standard type of crack or interface crack is considered in the context of classical fracture mechanics. To tackle this issue, the finite element mesh should keep the fixed size and shape at the location of interest where the singular point exists. This approach provides a simple way for relative stress comparison in different designs, although the absolute value of stress components has no actual meaning. In this paper, we also find that the peeling stress is in tension during cooling but in compression during heating, regardless of the material properties.

Finite Element Method for System-in-Package (SiP) Technology: Thermal Analysis Using Chip Cooling Laminate Chip (CCLC)

Abstract: We present in this paper a new modified version of the System-in-Package (SiP) model based on three-layer chips. The idea is to add copper layers permitting to take up its thermal dissipation and to investigate the thermal performance we have used Finite Element Method (FEM) analyses with COMSOL Multiphysics®. The temperature variation in the numerical simulation shows that the maximum temperature value is decreasing with a flat temperature distribution compared to the traditional model. Moreover, in terms of the thermal conduction performance, the thermal management of the system packaging, Chip-Cooling-Laminate-Chip (CCLC) is achieving high reliability and resolution with low-cost micro-devices especially for the micro-medicine applications, when the temperature maximum in the chips is reduced by 64%.

A Continuously Updated Package-Degradation Model reflecting Thermomechanical Changes at Different Thermo-Oxidative Stages of Moulding Compound

Abstract: Moulding compounds used for encapsulating electronics typically occupy a large portion of package volume and are most exposed to the external environment. Under harsh conditions such as high temperature, humidity, and mechanical vibrations, constituent materials of electronic components degrade, resulting in a change in their thermal, mechanical, electrical, and chemical behaviour. High-temperature ageing of electronic packages causes the oxidation of epoxy moulding compounds (EMC), forming a layer exhibiting significantly different thermomechanical properties. This reflects in the modified mechanical behaviour of the entire package, which accelerates certain failure modes and affects component reliability. Thus, it is crucial to consider gradual degenerative changes in EMC for a more accurate estimation of the component lifetime. This paper proposes a three-step modelling approach to replicate thermo-chemical changes in package encapsulation. A parametric geometry of a test package was incorporated with the ageing stage-dependent changes in thermomechanical properties of the oxidized layer. The mechanical behaviour of oxidized EMC at multiple stages of thermal ageing (at 150°C for up to 3000 hours) was first experimentally characterized and then validated using warpage measurements on thermally aged test packages and Finite Element (FE) simulations. Lastly, a trend-based interpolation of material model parameters for intermediate stages of ageing was followed, and a continuously updated degradation model (physics-based Digital Twin) was achieved. The proposed model is capable of reproducing degraded stages of the test package under thermal ageing along with its modified thermomechanical behaviour. Its limitations and significance in the domain of health monitoring of microelectronics are also discussed.

Modeling the Effects of Thermal Pad Voiding on Quad Flatpack No-lead (QFN) Components

Abstract: Finite element modeling was used to evaluate the effects of thermal pad solder voiding on the thermal resistance of Quad Flatpack No Lead components. This included two different approaches for modeling solder voids: many small, distributed voids, the effects of which were averaged across the entire solder contact area or a single discrete void. Two approaches were used for defining the thermal path established in the solder. The effects of other design parameters - thermal boundary conditions, the presence of thermal vias under the package, and the size of the die power dissipation area – were also addressed. Modeling showed that thermal vias and external boundary conditions had the most significant impact on the package thermal resistance. Solder pad voids and concentrated die-level heat dissipation, for the range used in this study, had noticeable but less significant impacts on thermal resistance. The study also compared different approaches for simulating solder voiding and identified ranges in which modeling simulations are most appropriate.

Impact of mechanical material modeling on the solder joint fatigue analysis of a leadless package mounted at different positions inside a generic aluminum ECU

Abstract: The solder joint fatigue lifetime of new microelectronics packages is usually experimentally evaluated using generic and unconstrained printed circuit boards (PCBs). In the later application, the PCB carrying the package may be constrained due to the mounting in a housing, which can adversely affect the solder joint fatigue lifetime. Solder joint fatigue simulation can be used as tool along the value chain to anticipate in an early phase a potential degradation of the solder joint lifetime and to evaluate countermeasures, such as a different placement of the package on the PCB inside the housing. The accuracy of the simulation will depend on the quality of the package model passed along the value chain. This paper studies for a discrete power package different types of material modeling which could potentially be communicated along the value chain and their impact on the accuracy of the prediction. All investigated descriptions correctly identify the most critical mounting positions of the discrete power package inside a generic model of an electronics control unit (ECU). The highest accuracy of the prediction is obtained with a non-linear and temperature-dependent material description of the package, followed by an approach using homogenized blocks with effective non-linear material properties are used. For linear-elastic properties, high deviations w.r.t. the non-linear case are observed in case constant properties over temperature are used and the glass transition region of polymers is passed though in the temperature profile of interest. Linear-elastic temperature-dependent properties are identified to be more accurate than linear-elastic constant properties, but are found to deviate in their estimations up to 25% compared to the non-linear material modeling.

Characterization of Packaging Stress with a Capacitive Stress Sensor Array

Abstract: This paper presents a high-resolution capacitive stress sensor array to precisely characterize the distributed MEMS packaging stress, for the first time. The unit stress measurement cell utilizes a bridge-type mechanical amplifier that converts the substrate strain into capacitance variations. We have measured and compared the MEMS die stress over temperature for different die attaches with a custom designed PCB housing an on-chip heater. The proposed approach significantly simplifies the evaluation and selection of packaging materials. Comparing the temperature responses of a soft silicone-based and stiffer silver-filled epoxy reveals difficult to predict results.

An Advanced Finite Element Model of the Cu Pillar Solder Reflow Assembly

Abstract: The recently emerged Cu pillar technology has drawn a lot of attention in the wafer-level packaging field due to its fine pitch and superior electrical performances. Flip-chipping Cu pillar dies to low-cost PCBs is considered a promising and cost-effective packaging approach. This paper focuses on developing a thermal-mechanical finite element model to identify how different Cu pillar and board configurations impact Cu pillar shear stresses. Furthermore, this model extracts shear stresses from Cu pillar solders in various positions, providing valuable information about Cu pillar shear strengths when compared to the visual inspection results of the package’s cross-section. This model is a significant step towards the further development and standardization of the Cu pillar flip-chip technology.

Studying Asymmetric Warpage Behavior of Panel-Level Packages Using Process Modeling Techniques and Viscoelasticity Theory

Abstract: Panel Level Packaging (PLP) is an integrated circuit (IC) packaging technology that is mainly used in fields such as mobile communications, consumer electronics, and industrial automation. Compared to wafer-level packaging, the advantages of panel-level packaging include improving manufacturing efficiency, reducing costs, and improving product quality. However, because the overall area of panel-level packaging is larger, there may be some problems in the manufacturing process, such as insufficient flatness of the substrate surface, poor adhesion between the substrate and the components, and incorrect component positioning. These problems may lead to poor product quality, asymmetric warpage, and even packaging failure.This paper aims to discuss the factors that may cause warpage in the panel-level packaging (PLP) process, including material non-uniformity, thermal stress, and mechanical stress. To address these issues, design and optimization of the packaging, selection of appropriate materials and process parameters, and stress analysis and simulation of the packaging are required. Through simulation, the warpage variation and stress distribution during the manufacturing process can be analyzed more efficiently. Our research will investigate the effects of different process parameters, such as the temperature of the molding process and the heating/cooling rate, as well as the thickness, size, and distribution of the encapsulant chips and other layers on warpage.

Polymer‐based nanocomposites in semiconductor packaging

Abstract: Semiconductor packaging materials play a critical role in the development of semiconductor devices. They not only provide reliable protection and support, but also contribute to the electrical connection between the chip and the external circuit. Among many choices of packaging materials, polymer-based nanocomposites have become the mainstream candidate due to their low cost, easy processability, and tunable properties. Materials with low dielectric constant and dielectric loss, high glass transition temperature, fast thermal conductivity, suitable coefficient of thermal expansion, low viscosity, and good processability are commonly required in semiconductor packaging, yet most polymers do not meet these criteria. Therefore, modulation of the polymer matrix, introduction of suitable fillers, and modification of the filler surface are often effective approaches to enhance the performance of the composites. Here, the authors first review current research progresses of polymer-based nanocomposites for five different types of packaging applications, namely moulding compounds, thermal interface materials, underfills, die attach materials, and substrates. The authors then present prospects of developing next-generation polymer-based nanocomposites for advanced semiconductor packaging and propose some suggestions to solve the existing challenges.

Analysis and improvement on cracking failure of glass sealed surface mount diodes

Abstract: With development of electronic equipment to miniaturization and lightweight, the demand for miniaturization chip devices is increasing. Because glass encapsulation devices are prone to damage, circuit faults often occur. In this paper, according to the typical failure phenomenon caused by the cracking of glass packaging surface diode, the cracking failure reason analysis and relevant test verification are carried out, which provides useful basis for further improving the reliability of glass packaging surface diode.

A Study of Underfill Dispensing Patterns in Flip-Chip Packaging

Abstract: In view of the continuous growth of digital-twin in the technology and industry in recent years, this study conducted the digital mapping of the underfill dispensing process through experiment and simulation to understand and solve the void problem that frequently occurred in flip-chip packaging.