Showing papers on "Emulation published in 1986"

Emulation process having several displayed input formats and output formats and windows for creating and testing computer systems

Abstract: A method of operating a computer system is disclosed that facilitates the creation and testing of application system software by utilizing an autonomous environment to emulate the application system environment. The emulation environment allows the user to call into view sequences of standard input-output (I/O) screen format pairs normally used to submit information to and receive information from the application system. In the emulation mode, these screens are prepared off-line and stored until the user desires to exercise the application system. Each input format is filled with information that will serve as actual input to the application system when it is exercised. Each output format is filled with information that comprises expected results when the application system is actually exercised. The expected results are compared to actual results after execution of each I/O pair and further application system processing is controlled by the comparison results. The stand-alone emulation environment provides editing and control routines and library functions to aid the user in defining and modifying the I/O sequences.

Roving Emulation as a Fault Detection Mechanism

Abstract: In this paper we present a new built-in test methodology for detecting and locating faults in digital systems. The technique is called roving emulation and consists of an off-line snap shot type emulation or simulation of operating components in a system. Its primary application is in testing systems in the field where real-time fault detection is not required. The primary performance measure of this test schema is taken to be the expected value of the error latency, i.e., the time required to detect a fault once it first occurs. The primary results of this paper deal with deriving equations for the error latency. We present both a probabilistic and service-waiting model to analyze the expected error latency in a system tested via roving emulation. The effects of various controllable and uncontrollable system parameters on error latency are studied. Finally, the technique is applied to a system consisting of combinational logic modules, and numerical results are presented.

Simulation of large networks on smaller networks

Abstract: Parallel algorithms are normally designed for execution on networks of N processors, with N depending on the size of the problem to be solved. In practice there will be a varying problem size but a fixed network size. In Fishburn and Finkel (IEEE Trans. Comput. 31 (1982), 288–295), the notion of network emulation was proposed, to obtain a structure preserving simulation of large networks on smaller networks. We present a detailed analysis of the possible emulations for some important classes of networks, namely: the shuffle-exchange network, the cube network, the ring network, and the 2-dimensional grid. We also study the possibility of cross-emulations, and characterize the networks that can be emulated at all on a given network using some class of emulation functions.

Peripheral emulation apparatus

Abstract: Control apparatus allows application software written for use with peripheral devices manufactured by one company to run with other peripheral devices. The apparatus intercepts device-specific control commands generated by the software and translates the commands into commands which are compatible with the peripheral connected to the system. Non-device specific commands are passed untranslated through the control apparatus to the peripheral. More specifically, registers within the control apparatus which must be programmed with parameters unique to a particular peripheral cannot be accessed by the application software while other nonspecific registers remain read and write accessible. Peripheral-specific parameters are instead changed by a secondary processor which uses special hardware to minimize interference with the main processor.

Addressing multiple storage spaces

Abstract: In a data processing apparatus, having a user domain with domain storage space and an emulation domain with emulation storage space, emulates an instruction in the user domain by calling a program of instructions in the emulation domain. An instruction register connected to receive the sequence of instructions is partitioned into a plurality of fields. At least one field of the instruction register identifies a location for address information for an operand used in execution of the instruction. The instruction is decoded to generate a control code. The control code includes a branch signal to call the emulation program and a domain access control signal to indicate whether the emulation program requires access to the user domain storage base for execution. During execution of the emulation routine, domain access is implied by the location identified for the address information--a set of locations having been preselected as address registers for implied domain addressing.

Microcomputer development system

Abstract: A development system for a family of one-chip microcomputers which are all of the same architecture but differ in the memory size and the input/output number, comprises a common emulation chip having the largest memory size and the largest input/output number in the microcomputer family, an information memory storing a data memory area utilizable in a target microcomputer to be developed, a local emulation chip for emulating the peripheral hardware of the target microcomputer, and a guard controller generating a guard verify signal for stopping an emulation operation when the access is made to a memory area or a peripheral hardware which is not to be included in the target microcomputer. Thus, the access to the resources which is not to be included in the target microcomputer is inhibited.

Different architecture emulation system

Abstract: PURPOSE: To attain emulation of a difference instruction in an OS by detecting the difference instruction at the execution of a program so as to generate interruption in executing the program generated for different architecture while the OS management as a task. CONSTITUTION: A fetch circuit 5 is provided between a CPU 1 and a main memory 2 and the operating system (OS) enables the circuit 5 just before a software developed for similar architecture is executed. Moreover, when a fetch signal 9 is given from a CPU 1, the fetch circuit 5 loads an instruction from a memory 2 into the circuit 5 and when the instruction is the difference instruction, the CPU 1 fetches the interruption instruction of the CPU 1 to generate interruption. Thus, the instruction being an object in the OS is analyzed to attain emulation. COPYRIGHT: (C)1988,JPO&Japio

A 32b single-chip microprocessor

Abstract: This paper will present a 32b single-chip microprocessor implementing 102 mainframe instructions and supporting the emulation of the rest of the instructions. The chip, 10mm × 10mm with 200,000 transistor sites, is designed for 10MHZ worst case and operates at 16MHZ with 3W dissipation.

Emulator for single-chip microcomputer

Abstract: PURPOSE:To realize high-speed emulation, by providing a counter at the outside of an ever-chip and, when a program fetching signal is outputted, supplying the content of the counter to an emulation memory as an address. CONSTITUTION:When an ever-chip 11 executes a program for the first time or immediately after a branch instruction is executed, an address presetting signal 2 is activated and the address of the first or branched program is outputted onto an address/data bus 7, and then, the address is preset in a counter 13. When a program fetching signal 3 is activated thereafter, the counter 13 is selected and the preset address is outputted to an emulation memory 12 through a bus 8. Simultaneously, a drive-enable signal is activated and data in the emulation memory 12 are outputted to the bus 7 through a buffer 15, since a memory write signal 6 is inactivated. If the program fetching signal 3 becomes inactive under this condition, the content of the counter 13 is increased by '1'. Thereafter, the content of the counter 13 is continuously increased unless a branch instruction is executed.

Development of an emulation-simulation thermal control model for space station application

Abstract: Analysis techniques to evaluate the effects of changing thermal loads and the methods utilized to control temperature distributions in the orbital space station are essential. Analysis techniques including a user-friendly computer program, were developed which should prove useful in thermal design and system analysis of the the space station. The program uses a data base and user input to compute costs, sizes, and power requirements for individual components and complete systems. User input consists of selecting mission parameters, selecting thermal acquisition configurations, transport systems and distances, and thermal rejection configurations.

The Literature of CAD in Magnetics

Abstract: Design is an art and must be studied through examples like any other art. Engineering design naturally includes a large element of engineering science, which is best acquired in an analytic and deductive fashion. Expertise in the art of design, on the other hand, is best learned by case studies and by emulation of others. To aid the reader in finding examples related to specific classes of problems, this bibliography is provided.

Design of testbed and emulation tools

Abstract: The research summarized in this report was concerned with the design of testbed and emulation tools suitable to assist in projecting, with reasonable accuracy, the expected performance of highly concurrent computing systems on large, complete applications. Such testbed and emulation tools are intended for the eventual use of those exploring new concurrent system architectures and organizations, either as users or as designers of such systems. While a range of alternatives was considered, a software-based set of hierarchical tools was chosen to provide maximum flexibility, to ease in moving to new computers as technology improves and to take advantage of the inherent reliability and availability of commercially available computing systems.

Esl - advanced simulation language for parallel processors

Abstract: This paper reports the results of a software engineering project entitled “Simulation Algorithms for Parallel Processes” which was carried out under European Space Agency (ESA) Contracts 4790/81 and 5663/83. The objective of the project was to produce computer programs to implement an advanced continuous-system simulation language (CSSL). The language, which has become known as ESL (ESA Simulation Language), is characterised by its advanced programming concepts. These include separate program units to describe the system and the experiment to be performed on it; modular model concepts in the form of submodels to define independent parts of the system; a segment facility which allows sections of the system to be simulated on a parallel processor emulation; techniques for conveniently describing and handling system discontinuities; and modern programming structure features with comprehensive procedural code facilities. The implementation provides both an interpreter version for fast turn-round of simulation programs under development, and a translator version for efficient production runs of developed programs.

Shared Memory Emulation Algorithm for Multiprocessors.

Abstract: This paper describes a library package that allows FORTRAN programs written to run on the Cray T3D using the get/put communication routines to be compiled and run on single and multiprocessor SGI systems. This package allows parallel programs to be developed on easily available SGI workstations and servers and later run with Grand-Challenge size problems on large T3D machines. This library is a subset of the libsma library of communication routines available on the T3D. In addition, the package allows the programmer to improve performance by directly exploiting the physically distributed local cache memories on the SGI processors.

A flexible architectural study methodology

Abstract: An efficient emulation/simulation system for evaluating architectures and scheduling strategies for reduction systems is described. Execution traces of example programs are generated by the emulator. The execution method of the emulator exercises all possible parallelism available in the execution model under study. The trace of each program execution is then reduced to an “architecturally neutral” precedence graph. The precedence graph can then be used repeatedly in simulations to study the effects of changes in architecture or scheduling strategy.

In-circuit functional or emulation - choosing the right test solution

Abstract: This paper provides an overview of the current developments in general-purpose automatic test equipment (GPATE) and examines some of the pitfalls in its use. It reviews the range of types of GPATE currently available, explores the latest developments in GPATE technology and looks ahead to some of the advances in digital and analogue techniques, as related to the needs of GPATE systems.

Emulators; prospective instruments for instruction in systems programming

Abstract: Microprogramming is a technique for implementing machine language instruction sets -- it is critical in today's computer architectures and operating systems. An emulator is a set of microprograms that implements the architecture of one machine on another; microprogramming is often used in emulation to make one computer system appear as if it were another. This paper presents the architecture for a microprogrammed computer system, the VSEM. The simulated virtual computer system, its monitor and a simulated concurrent PASCAL are discussed. The usefulness of the VSEM, its monitor and the concurrent PASCAL as vehicles for instruction in systems programming is addressed.

Program rom emulator

Abstract: PURPOSE:To make it possible to simply emulate large capacity program ROM, by performing the transmission of data by judging whether the address added from a target apparatus is present in the area of emulation memory CONSTITUTION:The address signal line of a target apparatus TA picked up by a probe P1 is added to a jumper block J and converted so as to coincide with the address arrangement of emulation memory EM An address selector AS compares this address data with the address area data of the emulation memory EM and, when said address data is out of the area, buffer memory BUFA is made effective and, when in the area, BUFB is made effective By this method, the transmission of data is performed between the target apparatus TA and the emulation memory EM through the buffer memory BUFB and the emulation of a program ROM can be performed

Emulators: prospective instruments for instruction in systems programming

Abstract: Microprogramming is a technique for implementing machine language instruction sets --it is critical in today's computer architectures and operating systems. An emulator is a set of microprograms that implements the architecture of one machine on another; microprogramming is often used in emulation to make one computer system appear as if it were another. This paper presents the architecture for a microprogrammed computer system, the VSEM. The simulated virtual computer system, its monitor and a simulated concurrent PASCAL are discussed. The usefulness of the VSEM, its monitor and the concurrent PASCAL as vehicles for instruction in systems programming is addressed.