Showing papers on "Emulation published in 1992"

Method and apparatus for debugging reconfigurable emulation systems

Abstract: An improved electronic design automation (EDA) system employs field programmable gate arrays (FPGAs) for emulating prototype circuit designs. A circuit netlist file is down-loaded to the FPGAs to configure the FPGAs to emulate a functional representation of the prototype circuit. To check whether the circuit netlist is implemented properly, the FPGAs are tested functionally by applying input vectors thereto and comparing the resulting output of the FPGAs to output vectors provided from prior simulation. If the FPGAs fail such vector comparison, the FPGAs are debugged by inserting "read-back" trigger instructions in the input vectors, preferably corresponding to fail points in the applied vector stream. Modifying the input vectors with such read-back signals causes the internal states of latches and flip-flops in each FPGA to be captured when functional testing is repeated. Such internal state information is useful for debugging the FPGAs, and particularly convenient because no recompilation of the circuit netlist is required. A similar approach which also uses the read-back feature of FPGAs is employed to debug FPGAs coupled to a target system which appears to fail during emulation runs.

An efficient logic emulation system

Abstract: The Realizer, a system which automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. The interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales linearly with pin count, and allows hierarchical expansion to systems with hundreds or thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 XC3090 FPGAs for logic. A 32-b CPU datapath has been automatically realized and operated at speed, and demonstrates very good FPGA utilization. >

Methods of monitoring the status of an application program

Abstract: An application or terminal emulation program, which is being executed on an information processing system, is represented by the display of a first icon on a display device. If during the execution of the application or terminal emulation program, a virtual display buffer associated with the application program, is updated, a second icon is displayed on the display device to indicate to a user of the system that a change in the status of the program has occurred.

Fast mutual exclusion for uniprocessors

Abstract: In this paper we describe restartable atomic sequences, an optimistic mechanism for implementing simple atomic operations (such as Test-And-Set) on a uniprocessor. A thread that is suspended within a restartable atomic sequence is resumed by the operating system at the beginning of the sequence, rather than at the point of suspension. This guarantees that the thread eventually executes the sequence atomically. A restartable atomic sequence has significantly less overhead than other software-based synchronization mechanisms, such as kernel emulation or software reservation. Consequently, it is an attractive alternative for use on uniprocessors that do no support atomic operations. Even on processors that do support atomic operations in hardware, restartable atomic sequences can have lower overhead.We describe different implementations of restartable atomic sequences for the Mach 3.0 and Taos operating systems. These systems' thread management packages rely on atomic operations to implement higher-level mutual exclusion facilities. We show that improving the performance of low-level atomic operations, and therefore mutual exclusion mechanisms, improves application performance.

Shared bus in-circuit emulator system and method

Abstract: An in-circuit emulator, alternatively referred to as a microcontroller debugging system, has a control processor having I/O ports and a multiplexed address/data bus port, an emulation processor having I/O ports and a multiplexed address/data bus port, an emulation memory having address inputs, a data bus interface and a plurality of two-to-one multiplexers. The in-circuit emulator is configured such that the control processor and the emulation processor each have at least one port directly coupled to the data bus of the emulation memory without the use of external tri-state buffers, this is referred to as the shared bus. An address latch, shared by both processors, has its inputs coupled to the shared bus. The outputs of the address latch form a portion of the emulation memory address input, and are coupled to a corresponding portion of the emulation memory address inputs. The emulation processor is supplied with a clock which is selected from the group consisting of: the same clock input signal used by the control processor, a clock synchronized with the internal clock of the control processor and a clock which is asynchronous with respect to the internal clock of the control processor.

Image forming device

Abstract: PURPOSE:To print optimum image required by user all the time CONSTITUTION:When data from a host device is character data, a descriptor for constituting pages is formed When it is a command other than an emulation switching command or control code, a process corresponding to it is performed When it is the emulation switching command, it is determined whether a pointer PTR pointing a head of the descriptor is '0' or not When PTR='0', the emulation is switched immediately When PTRnot equal to '0', it is determined whether an overwrite mode is a forced output mode or not If it is the forced output mode, pages are constituted based on the descriptor made till then It is printed out and the emulation is switched If it is the overwrite mode, the emulation is merely switched in order to add it to the descriptor made till then

Electronic systems and emulation and testing devices, cables, systems and methods

Abstract: An electronic system for use with a host computer. The system includes electronic circuitry including a first semiconductor chip generally operable for a first function and also adapted for input and output of emulation signals. This is combined with emulation circuitry including a second semiconductor chip adapted for connection to the host computer. The emulation circuitry is connected to the electronic circuitry to generate emulation signals to input to the electronic circuitry and to accept emulation signals from the electronic circuitry. A physical assembly supports the emulation circuitry and the electronic circuitry as a unit. Other electronic systems and emulation and testing devices, cables, systems and methods are also disclosed.

Data processing devices, systems and methods with mode driven stops

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Computing with faulty arrays

Abstract: We present and O(1) slowdown emulation of a fault-free N x N two dimensional mesh with a slack of O(log N log log N) by a faulty mesh of the same size and slack. All components of the faulty mesh, including the memory modules, are assumed to be subject to failure. The faults may occur at any time during the emulation and the system readjusts dynamically.

Digital neural emulators using tree accumulation and communication structures

Abstract: Three digital artificial neural network processors suitable for the emulation of fully interconnected neural networks are proposed. The processors use N/sup 2/ multipliers and an arrangement of tree structures that provide the communication and accumulation function either individually or in a combined manner using communicating adder trees. The performance for the emulation of an N-neuron network for all processors is achieved in 2log/sub 2/N+C time units, where C is a constant equal to the multiplication, neuron activation, and internal fixed delays. The feasibility and characteristics of the proposed configurations to emulate single and/or multiple neural networks simultaneously are discussed, and a comparison with recently proposed neurocomputer architectures is reported. >

Using negative stuffing retiming for circuit emulation in a packet switching network

Abstract: A circuit emulation scheme based on negative stuffing retiming that can effectively remove large bursty delay between packets is described. The approach can be applied to various applications such as T-carrier emulation and packet voice and video communication. The key element of the proposed negative stuffing scheme is the stuffing control or when to add negative stuffing. Two stuffing control algorithms are discussed. The first one is very simple and can provide a smooth output without the need of knowing or estimating the transmitter clock. This algorithm transforms large and fast packet arrival jitter into small and slowly varying frequency wander. The second algorithm tries to estimate the transmitter clock to further reduce the wander. Both algorithms will in principle eliminate the large packet arrival jitter completely, and they also ensure no buffer overflow and underflow. To evaluate buffer delay, jitter, and wander of the recovered clock, time domain simulation has been done for DS1 and DS3 signals over a SONET STS-3c-based switching network. >

Information processing method and apparatus

Abstract: An information processing apparatus comprises: a memory to store emulation information which is designated from a host computer that is connected to a printer via a general parallel interface; a judging circuit to judge a delimiter of print data; and a control unit to switch the emulation on the basis of the emulation information stored in the memory and the result of the judgment by the judging circuit. When each section of the apparatus is in the inoperative state, they are set into the power saving mode and are sequentially controlled. Thus, the power saving of the whole apparatus can be realized.

Traffic patterns in a scalable multiprocessor through transputer emulation

Abstract: The authors present a multiprocessor emulator designed to evaluate a scalable shared virtual memory architecture called the Data Diffusion Machine (DDM) The DDM is characterised by the lack of any fixed home location for data, with the virtual address being completely decoupled from the physical location of a datum The authors describe the design of the emulator for the DDM and its transputer-based implementation The emulator provides a flexible platform for evaluating the architecture and enables one to study the overall behaviour of the machine while running real, lace shared-memory applications They present a profile of traffic observed at the controllers in the DDM hierarchy while running a variety of real shared-memory applications >

Benchmark workload generation and performance characterization of multiprocessors

Abstract: A comprehensive benchmark workload generation and performance characterization methodology is described for multiprocessors supporting the shared-variable computational paradigm. The method can be tailored to meet the selective assessment needs of each individual situation. The approach is based on characterizing a unit grain of computation to generate a desired benchmark workload, and using a family of workload emulation kernels to systematically investigate the effect of each parameter in the workload on the multiprocessor performance. The resultant characterization is independent of any particular application or algorithm. >

Transaction system emulator

Abstract: A transaction system emulator serves to emulate various transaction system peripherals, replacing each emulated hardware peripheral by a corresponding software counterpart and an interconnection between the computer performing emulation and the transaction system hardware. Thus, one or more input devices (102) are replaced with logs of input data (105) such that the system being emulated can be tested without requiring a significant amount of input test data to be manually entered. Sets of test data may be captured either utilizing the emulator system with actual peripheral input devices (102), or obtained from an actual transaction system including such input devices. Alternatively, input test data logs (105) are created by other means, such as by a program, text editor, or the like. An output log of data resulting from input test data is created and, if desired, compared against a log of known, valid data corresponding to the input test data.

A digitally implemented modem - Theory and emulation results

Abstract: Theory and hardware emulation results are presented for a very flexible digitally implemented modem whose technology is useful over a broad class of terrestrial and in-flight satellite communications applications. The interdependent detection and tracking loop architectures based on the 'joint estimator-detector' approach is shown to perform well for various modulation techniques. The analysis is accurate in setting the loop parameters, and also predicting their transient behavior.

Circuitry and method for causing a microcontroller/microprocessor to be on-circuit emulated

Abstract: An emulation system for performing an on-circuit emulation operation of a component in a data processing system is described. The component includes a plurality of pins coupled to the remaining circuitry of the data processing system. An emulator is coupled to the remaining circuitry in the same manner as that the component is coupled to the remaining circuitry for issuing an on-circuit emulation control signal to one of the plurality of pins of the component to place the component in an on-circuit emulation mode and for performing the on-circuit emulation operation of the component. A reset circuit is coupled to a reset input of the component and a reset input of the emulator for generating a reset signal to reset the component and the emulator. When the reset signal is in a first voltage state, the component and the emulator are in a reset state. When the reset signal reaches a second voltage state, the component and the emulator exit the reset state. A comparator is coupled to receive the reset signal and a reference voltage for causing the emulator to generate the on-circuit emulation control signal to the one of the plurality of pins of the component when the reset signal is in the first voltage state, and for causing the emulator to maintain the on-circuit emulation control signal applied at the one of the plurality of pins of the component until after both the component and the emulator are out of the reset state such that the component can enter the on-circuit emulation mode and the emulator can start the on-circuit emulation operation after both of the component and the emulator exit the reset state. The voltage level of the reference voltage is higher than the second voltage state of the reset signal. A method of placing the component in the on-circuit emulation mode is also described.

The anthroform neural controller: a system for detailed emulation of neural circuits

Abstract: The authors describe a versatile parallel computing architecture for emulating the spinal circuits of the human nervous system. When used in conjunction with a dynamically realistic replica of the human arm, this controller will provide a versatile tool for studying human motor-sensory control. The design is based on the structural constraints of the nervous system, and consists of a special purpose digital bus which implements connections between simulated neurons running on TMS 320C30 digital signal processors (DSPs). The system supports up to 1024 individual neuron models, each connected to every other one at least once every millisecond. These neuron models may be distributed over as many as 256 processor circuit cards, each supporting an interface for high level control from a host and another for input and output functions. >

High-level synthesis in a rapid-prototype environment for mechatronic systems

Abstract: The application of high-level synthesis techniques onto a rapid-prototyping board is presented. The board is part of a design methodology that supports the development of embedded information processing units in mechatronic systems during early design phases. The spectrum of realizations ranges from single task software implementations on a single board computer to an ASIC emulation in a heterogeneous multiprocessor environment. Emphasis is on the automatic synthesis of hardware modules to be realized as ASICs. A synthesis environment is presented which automatically maps modules to be implemented as ASICs onto a rapid-prototyping board. >

Microcomputer and emulator

Abstract: PURPOSE: To provide the microcomputer to be used as a processor for emulation corresponding to the plural kinds of microcomputers by using the processor for emulation composed of the same chip as the microcomputer of a specified real chip CONSTITUTION: Memory capacity or the validity/invalidity of an incorporated function block can be independently designated by adopting a control register 9 for selecting which microcomputer is provided with the microcomputer for emulation The microcomputer for emulation is provided corresponding to the single chip microcomputer, which does not incorporate the program ROM of a central processing unit 2, and the various kinds of single chip microcomputers with built-in ROM can be dealt with COPYRIGHT: (C)1994,JPO&Japio

Emulation framework for testing higher level control methodology

Abstract: : Emulation is defined as an intermediate stage of simulation where the model represents the 'as specified' mechanical plant and equipment, but not the control logic required to drive it. This thesis investigates the utility of providing a computer representation of the functional elements to be controlled by system control programs. These representations or 'emulators' mimic the behavior of the system, or factory being controlled. The advantages of such a scheme are that developers of control software, are able to test out new control methodologies without actually connecting to the hardware system under control. This thesis investigates system control for automated manufacturing systems and identifies how emulation can be used as a valid tool in reducing the implementation time of such systems. The functions and characteristics of system control are identified as well as the problems associated with their implementation. The problems are then categorized to identify where emulation is a valid tool for problem resolution. This thesis is concluded by a description of a software demonstration which validated the concept of using emulation to solve system control problems.

Remote console emulation system for a computer system

Abstract: of EP0520768A remote console emulation for a computer system manager operates by transferring video screen images from system memory to the remote console and by inserting keystrokes from the remote console into the system keyboard controller. This emulation constitutes a marked improvement over prior art emulations because it does not require software on the host system.

Design verification of a high density computer using IEEE 1149.1

Abstract: This paper discusses the use of the IEEE 1149.1 test bus, internal scan and built-in emulation logic in the design verification and system integration of an embedded 100Mhz high density scalarlvector parallel processing computer.

Efficient parallel simulation for designing multiprocessor systems

Abstract: Simulation has emerged as the primary means for evaluating the design of multiprocessor systems. Simulation of such systems has become increasingly time-consuming because of the increasing complexity of the interactions between components of the systems and the need to simulate large parallel programs to obtain accurate performance prediction. The objective of this thesis is to develop fast efficient simulation techniques that can reduce simulation time sufficiently so that the performance of large parallel programs can be examined in a reasonable time. Such techniques when incorporated in simulation tools will reduce design time, improve multiprocessor designs, and enable the concurrent development of optimized multiprocessor software. SIMPLE (Simulation Instrument for Multiprocessors at Program Level using Emulation), a software package for simulating multiprocessor systems efficiently, uses high-resolution clocks on the host systems to directly obtain the timing of code-segments. SIMPLE automatically instruments parallel programs, directly executes the instrumented programs, and incorporates architecture parameters. SIMPLE usually takes no more than 2 instructions to simulate 1 instruction, compared to 300 or more for accurate instruction-level simulators. Techniques were developed to parallelize multiprocessor simulators. The importance of dynamic topological information and global simulation information was identified, and the DLC (Dynamic Logical Channel) and DAI (Direct Access of Information) schemes were developed to exploit this information. In the DLC scheme, parallel programs are analyzed and instrumented before simulation. During simulation, information on the interactions between execution threads in gathered. By exploiting this information, the set of possible interactions is limited and simulation parallelism is improved. The DAI scheme aggressively collects useful simulation information in shared-memory multiprocessor hosts to reduce nonessential blocking and resolve local deadlocks. The simulation overhead of collecting information is reduced by search-pruning techniques. The DLC and DAI schemes were used to parallelize SIMPLE. A prototype of parallel SIMPLE was constructed on the Sequent Symmetry multiprocessor.

A Multiprocessor Architecture For Real-time Emulation Of Management And Control Of Broadband Networks

Abstract: An Architecture for real-time monitoring and Control of Broadband Networks is presented. It embeds the Management, the Traffic Control and the Information Transport Architectures. A multiprocessor real-time Emulator is developed in order to evaluate the correctness and performance characteristics of the model. The Emulator provides functions for real-time traffic generation, information transport and storage. It implements the Traffic Control Architecture as a set of distributed algorithms that exchange information through the Network Database. A Network Management Center is used to implement OS1 management protocols and to present network operating information in real-time.

Computer system having software interrupt (intn) instructions selectively operating in a virtual mode

Abstract: A computer system is disclosed herein including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing software interrupt (INTn) instructions, using emulation software forming part of the host program in order to emulate the way in which these instructions would have been executed by the earlier microprocessor. As a unique improvement to this overall computer system, certain ones of the INTn instructions are executed by means of emulation software while others are executed by means of the previously written program in cooperation with the given microprocessor and its host operating software program.

Microcontroller with provisions for emulation.

Abstract: For use in emulation a non-bond-out microcontroller has in-microcontroller multiplexing means for multiplexing a port among user data and program store addresses. It has a multistate machine cycle with plural clock pulses per state. Various additionally provided emulation pins allow for outputting any or all of the following signals: a start-of-cycle pulse indicating non-sleep mode a state-wise recurrent signal signalling progress of said states during non-sleep mode a signal discriminating between idle and reset a multiplexed signalization among any or all of the following: that a next-following machine cycle is the first of a next instruction; that presently an interrupt is being processed; that an external program memory access is forthcoming; that an external data memory access occurs; that an external data memory write access occurs. h