Showing papers on "Fault indicator published in 1979"

Online digital fault locator for overhead transmission line

Abstract: The ability to determine quickly and accurately where faults have occured on a transmission line has long been an operating man's dream. This paper describes a completely digitalised online fault locator which takes input signals from existing c.t.s and p.t.s and works on a reactance-ratio-measurement principle. It operates in less than two cycles from the instant that the relay delivers a trip output, and is therefore capable of locating transient as well as permanent short-circuit faults. Furthermore, a suitable compensation in fault-locator inputs is proposed which results in increased resistive coverage for the suggested fault locator when applied to double-end feed lines.

Fault dictionary based upon stimulus design

Abstract: A method of fault signature generation is presented that is based upon state space analysis of linear circults. An input control sequence is designed to reduce a nontrivial initial state of the circuit under test to the zero state in finite time. The realization of this stimulus as a piecewise constant waveform has step amplitudes that are exponential functions of the poles of the circuit under test. Perturbations of these amplitudes, engendered by element drift failure, constitute a fault signature. Single element value perturbations engender fault signature trajectories in signal space, and the fault dictionary is constructed by defining disjoint decision regions (hypervolumes) around each fault signature trajectory in the signal space. Circuit zeros of transmission allow the dimension of the signal space to be augmented with perturbation of such response waveform parameters as zero crossings. The theory of stimulus design for fault isolation in linear networks and a generalized matrix inverse method for computing the stimulus amplitudes from the pulse response of strictly proper circuits are presented. Examples of response waveforms and fault signature trajectories are given for several circuits.

Structure for physical fault simulation of digital logic

Abstract: A shift register connected to elementary gates is added to a digital network to form a fault simulator. The shift register and the additional gates can select a connection from the digital network and simulate a fault on the selected connection. Connection selection is done at a speed comparable to that at which the digital network operates and fault simulation is nondestructive. By resetting the shift register the fault simulator performs as if the digital network were fault-free. To simulate certain faults in the digital network a predetermined fault injection pattern for the faults to be simulated is entered into the shift register.

Fault detecting system for locating a fault point with a fault resistance separately measured

Abstract: At an end (11) of a power transmission line (10), a fault detecting system monitors variations resulting from a fault in voltage and current being transmitted through the line and calculates the distance between the end and location (20) of the fault by the use of the variations and a line constant inherent to the line, such as that given by the characteristic impedance and the propagation constant, to thereby locate the fault with a sufficient accuracy by directly using the commercial frequency and without affected by the impedance that accompanies the fault. The system can calculate the fault impedance from the distance and those backward impedances seen at the end and an opposing end (12) of the line backwardly of the location of fault.

Test point mounted circuit condition indicator

Abstract: Case 790314 TEST POINT MOUNTED CIRCUIT CONDITION INDICATOR Edmund O. Schweitzer Abstract of the Disclosure Indicating devices for mounting on a test point in an alternating current distribution system provide a visual indication of either voltage level or fault occur-rence in the system. The indicating devices are contained in a housing which includes an electrically-conductive rubber outer shell adapted to snap-fit over the test point, and a non-conductive inner housing within which the indicating devices are contained. The indicating devices include a bridge-type rectifier which is coupled to a con-ductor of the system through the test point terminal, and to ground through the electrically-conductive outer shell. In a voltage indicator application, the rectifier circuit charges a capacitor across which a neon lamp visible through a window in the end of the housing is connected the rate at which the neon lamp flashes providing an indication of the voltage level on the conductor. In a fault indicator application, the rectifier charges a capacitor which provides current for tripping an indicator flag to a fault-indicating position following a fault, and to a reset position upon restoration of alternating current in the system.

Multiple Fault Diagnosis in Combinational Networks

Abstract: The concept of prime faults is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a structurally equivalent fault with prime faults as its only components. Functional and structural masking and covering relations among faults are defined. These relations can be exploited to greatly simplify multiple fault analysis and their test generation. We present an efficient algorithm that generates a multiple fault detection test set and identifies redundancies. Suggestions for designing networks to yield a minimum number of tests in the multiple fault detection test set are also included.

Method for locating a fault point on a transmission line

Abstract: A fault component current is obtained in response to a fault at a fault point within a protective section on a transmission line at one end of the protective section. Assuming that a phase difference between the fault component current and a fault point current flowing through the fault point is known, the fault point current is obtained on the basis of the fault component current and the phase difference. Then, a voltage at an assumed fault point is obtained by using voltage and current at the one end of the protective section and the line constants of the protective section. An assumed fault point is then obtained to permit the voltage at the assumed fault point to be in phase with the fault point current. The assumed fault point is assumed to be a true fault point.

Generalised polyphase fault-analysis program: calculation of cross-country fault

Abstract: A general computer program using the phase co-ordinate technique has been developed for analysing series, shunt and simultaneous faults on balanced and unbalanced polyphase electrical networks. The program eliminates the need for maintaining numerous fault analysing subroutines, one for each kind of fault, and makes the solution of many difficult and previously unsolvable problems possible. It is employed to analyse the cross-country fault involving different phases. The solution method, program outlines and postfault results of voltages, currents and apparent power of an actual power system are given.

On Necessary and Sufficient Conditions for Multiple Fault Undetectability

Abstract: This correspondence states necessary and sufficient conditions for a multiple stuck-at fault in a combinational network to be undetected by a test set. The conditions are given in terms of fault masking relationships. It is shown that several other statements on this subject which have appeared in the literature are invalid.

An Ultrafast Fault Sensor for a Fault Current Limiting Device

Abstract: A power system fault current limiting device must act quickly if it is to limit the initial fault current.

On Analytical Modeling of Intermittent Faults in Digital Systems

Abstract: This correspondence discusses three analytical models for intermittent faults in digital systems. These models attempt to represent the stochastic behavior of intermittent faults accurately. The models find applications in predicting the performance of fault detection algorithms. A fault detection procedure is described and its performance is examined based on the analytical models. A numerical example is presented which illustrates the performance prediction of the fault detection algorithm.

A method of fault analysis and suppression of fault current in six-phase power transmission systems

Abstract: The case of infinitely large tertiary impedances for fault suppression in EHV and UHV transmission systems is discussed. Although the voltage rise of the sound phase in fault condition is considerably high, the almost-null fault control gives great advantages to the important (low-voltage) distribution lines. It is shown that: the fault analysis of a six-phase transmission line can be performed by the combined use of two- and three-phase symmetrical coordinate methods; the ground fault and short-circuited fault currents can be suppressed to the magnitude of the same order as the exciting current of the transformer; the induced electromotive force of the transformer winding of faulted phase is reduced to zero and therefore the arc ground fault current could be extinguished by itself; and the symmetric two-phase ground fault current reaches a considerably large magnitude (about one-half the single-phase line-to-ground fault current of conventional double-circuit three-phase transmission line) but its earth return component is almost zero if the ground faults on the two lines occur at the same point.

Fault diagnostic device for winding of electric machinery and apparatus

Abstract: A fault diagnostic device comprises vibrating means for vibrating a winding by feeding current having a predetermined frequency; detecting means for detecting physical value given in said winding by the vibration; and indicating means for indicating the result of the detection by said detecting means whereby a diagnosis of fault can be performed in high reliability.

Device fault recording circuit

Abstract: PURPOSE: To enable to point out a fault point with accuracy in correcting the fault, by recording diagnostic information such as periodic diagnostic information and enviromental information on device operation such as a voltage and frequency during the occurrence of the fault in a nonvolatile recording means, by equipping an output means of displaying the contents of a fault recording means. CONSTITUTION: A fault occurring to electronic device 1 is detected by fault detecting circuit 11 and while this fault data is sent to writing circuit 41, retrying circuit 13 is actuated to send its retry information to writing circuit 41 at the same time as well. Writing circuit 41 reads device environmental information on a voltage, frequency, temperature, humidity, etc., in the occurrence of the fault out of environment recording means 31 together with said information on the fault and retry and writes those pieces of information in nonvolatile memory means 42. A person in charge of maintenance, when repairing the electronic device during the occurrence of the fault, connects display means 51 and printer 22 direct to recording means 21 to print the information or display unit 23 direct to recording means 21 for display, so that he can easily obtain various hysteresis in nonvolatile memory method 42. COPYRIGHT: (C)1981,JPO&Japio

Visual printed wiring board fault detection by a geometrical method

Abstract: The algorithm described in this paper uses the geometric distance between con ductor boundaries as the criterion for a printed wiring board fault detection. A paging scheme is used so that only small parts of the picture need be stored in core. This also makes the method easily amenable to parallelism.

Method of and apparatus for transmitting information about flow of fault current in a faulty section of an electric power transmission system

Abstract: A method and an apparatus for indicating, at a receiver (37), the location of sections of a cable or line, in an electric power system, which have carried a fault current, by providing, for each section, a transmitter (20) including energy storage means charged by the fault current flow via a current transformer (16) and operative, on cessation of the fault current, to initiate, after a predetermined delay different for each section, the injection by transmitter (20) of a high frequency pulse signal into the cable or line (10, 11) also through the current transformer (16) so that, at the receiver (37), a record of the times of receipt of the signals identifies all the sections which have passed the fault current.

Power semiconductor protection circuit with fault detection

Abstract: A protection and fault detection circuit for an electrically isolated semiconductor power driver acting as a switch to connect a load such as a relay coil to a source of voltage employs logic circuitry responsive to input signals indicative, respectively, of the desired state of driver operation and the conductive condition of the driver itself to effect a rendering of the device to the nonconducting state when an overload or other fault condition exists. A monitoring circuit responsive to specified operating parameters of the semiconductor power driver and its associated circuitry provides an output fault signal which is indicative of a fault condition and may be employed for remedial and/or indicating purposes.

Ground fault protective circuit interrupter

Abstract: A fault current protection interrupter which is also sensitive to direct current operates less well in the presence of a strong A.C. fault current. According to the invention, the magnetic circulation resulting from an A.C. component of the fault current is compensated for in a core 12, by means of a suitable circuit, which is shown in dotted lines in Figure 7, in that a corresponding current is directed via a coil 1 of this core, as shown in Figures 1 and 7. This compensation current is a measure of the A.C. component. The core, in which there is no interfering, changing magnetic flux, is used to establish the D.C. component. The components of the D.C. fault current and of the A.C. fault current established in this way are transferred to a suitable evaluation circuit which initiates a disconnection if the values arising are not permissible.

On-line Fault Detection And Correction In Microprocessor Systems

Abstract: In most on-line diagnostic schemes whenever a fault is detected in a system, a rather involved system recovery routine is initiated irrespective of whether the fault is caused by a failure inside a chip, or by a failure outside a chip, say, on the bond connecting a pin to the chip. Failures of the latter type cause errors only when some information is being transferred from one chip to another chip. In this paper, 'two new techniques to system recovery are described for the case when an error is on any such data transfer path. These schemes are implementable locally, and the system is ensured to recover from any single stuck-at fault, single AND-bridge fault, or single OR-bridge fault in a single retry. The system- recovery from faults internal to chips can be per- formed using sophisticated routines. Thus, two- level approach to on-line system diagnosis seems to be more efficient.

Diagnosis of Faults in Modular Trees

Abstract: Diagnosis of stuck-at faults (s-a-f's) in modular trees is studied. Detection conditions for each distinguishable s-a-f in a module are derived. For single s-a-f's, the detection conditions are easily partitioned to achieve fault location by performing a small number of additional tests. A multiple s-a-f that produces the same test result as a single s-a-f can be located by applying additional tests whose number grows with the tree depth. All other multiple s-a-f's are detected but cannot be located. In this paper location algorithms for combinational modular trees are presented in detail. They are then modified to locate faults in modular trees which realize arbitrary definite machines. Since a pair of these tree structures can be connected to realize arbitrary sequential machines, the results derived here are useful in diagnosing sequential machines. The ability to diagnose faults, combined with the fact that the function of the tree is easily altered, makes this structure attractive in reconfiguration applications. In particular, application to array processors is suggested.

Fault detecting system

Abstract: PURPOSE:To secure an easy detection of the factor and the area for the fault with no error by making ineffective the function of other fault detecting means when a fault detecting means detects the fault. CONSTITUTION:Input signals FS1-FSn are checked through fault detectors D1 and so forth of fault detecting means DET1'-DETn', and the output signals are connected to fault indicator DSPF1 and so on which can perform resetting in terms of program via gate A1 and so forth along with output signal RSALL of OR circuit OR1 and also connected to OR1. As a result, if only one of DET1'-DETn' detects the fault and the fault is displayed on the fault indicator, the function of other fault detecting means is masked until the corresponding faulty indicator is reset even though the system may be confused therafter. Thus, the area of the first fault occurrence can be recognized easily.

Fault location in a noisy multiple-nonlinearity servosystem

Abstract: In certain applications it is desirable to isolate faults in a nonlinear system using dynamic measurements at a limited number of access points. This can be achieved by stimulating the system with a serial mode sinusoidal signal and using the fundamental and higher harmonic responses at the access points to form the system "signature." The fault signature is then compared with a restricted number of stored signatures of known faults via the nearest neighbor rule.

Power supply fault process system

Abstract: PURPOSE:To enhance the fault process function by classifying more than one unit of power supply unit to be used for the electronic computer or the like into the power supply group to maintain the main function of the unit and the power supply group having no effect to the main function and discontinuing the operation of the unit in the case of the fault of the former group and giving the fault display in the case of the fault of the latter group each. CONSTITUTION:Power supply 9, 10 ... 11 to be used for the electronic computer or the like are classified into the power supply group of 9, 10 ... to maintain the main function of the computer and the group of power supply ... 11 which has no effect to the main function respectively. The output of the former group is connected to OR curciut 3, and primary power switch 2 is controlled by fault output signal 4 of circuit 3 to end the operation of the unit in case some fault takes place to 9, 10 ... and fault signal 6, 7 ... are produced. While the output the latter power supply group ... 11 is connected to OR circuit 13, and the fault occurred at power supply ... 11 is displayed on fault indicator 14 by the output of circuit 13.

Comments on "Multiple Fault Detection in Combinational Network"

Abstract: In the above paper,1the authors have defined complete test, closed fault set, fault set graph, and undetected fault set as follows.