Showing papers on "Floorplan published in 1994"

Modern VLSI design

Abstract: From the Publisher: The state of the art in VLSI design: layouts, circuits, logic, floorplanning, and architectures New techniques for maximizing performance and minimizing power usage Extensive new coverage of advanced interconnect models, including copper Up-to-the-minute coverage of IP-based design Detailed HDL introductions: Verilog and VHDL The #1 VLSI design guide-now fully updated to reflect the latest advances in SoC design Modern VLSI Design, System-on-Chip Design, Third Edition is a comprehensive, "bottom-up" guide to the entire VLSI design process, focusing on the latest solutions for System-on-Chip (SoC) design. Wayne Wolf reviews every aspect of digital design, from planning and layout to fabrication and packaging, introducing today's most advanced techniques for maximizing performance, minimizing power utilization, and achieving rapid design turnarounds. Coverage includes: Advanced interconnect models: new techniques for overcoming delay bottlenecks, reducing crosstalk, and modeling copper interconnect Advanced low-power design techniques for enhancing reliability and extending battery life in portable consumer electronics Testing solutions for every level of abstraction, from circuits to architecture Practical IP-based design solutions A thorough overview of HDLs, including new introductions to Verilog and VHDL Techniques for improving testability, embedded processors, and more VLSI design for today's high-performance, low-power devices requires broader, deeper skills than ever before. Modern VLSI Design, System-on-Chip, Third Edition brings together those skills in a single, comprehensive resource that will be invaluable to every VLSI design engineer and manager.

Similarity-extraction force-oriented floor planner

Abstract: A method of making, including a method of floorplanning, an integrated circuit includes the separation of electrical logic function cells of the integrated circuit into sets or macros of data path cells, each of which evidence a high level of similarity or repetitiveness in the integrated circuit, and into sets of random logic cells, which each are connected to data path cells but which do not meet topological and connectivity criteria for the data path cells. The data path cells are iteratively sorted according to connectivity requirements and are initially placed on a provisional floor plan of the integrated circuit in a cell-space matrix of rows and columns, the rows being of substantially uniform width to accommodate functional modules of the data path cells, and the rows being of variably height to cooperatively define the spaces of the cell-space matrix. The random logic cells are also iteratively sorted according to connectivety requirements of the integrated circuit and are placed over the data path cells as a provisional overlay of the random logic cells, which are then fitted into any open spaces of the cell-space matrix, and are then inserted into either new rows or new columns of the matrix according to a shape-measuring of the overlay of random logic cells.

A genetic algorithm for floorplan area optimization

Abstract: The paper deals with the problem of floorplan area optimization; an approach based on genetic algorithms is proposed. The method produces optimal results with CPU time requirements comparable with the ones of other approaches but presents some advantages: it requires a limited amount of memory to store partial results, it is not sensible to special structures like nested wheels, it allows additional constraints to be easily taken into account, it allows the user to easily trade off CPU time with result accuracy, it is simple to implement. Experimental results on the biggest problems proposed in the literature are reported. >

Fuzzy partitioning applied to VLSI-floorplanning and placement

Abstract: Fast hierarchical optimization methods applied to VLSI-floorplanning and placement play a major role in advancing the state of the art in physical design, because circuits get more and more complex. This paper presents a new approach for floorplanning and placement using fuzzy logic as the framework for optimal partitioning. Two hierarchical partitioning strategies are described, both based on the fuzzy c-means algorithm (FCM), well known in the area of clustering and pattern recognition. The first method outlined is applied to a modified GORDIAN procedure, combining wire-length minimization by force directed relaxation (FDR) and a fast clustering technique instead of min-cut. The second approach outlined specifies different similarities between the cells using one fuzzy similarity relation for each feature. A simple example with 16 mesh connected cells and a benchmark example with 33 cells are given to demonstrate the performance of the strategy. >

Floorplan area optimization using genetic algorithms

Abstract: The paper deals with the problem of Floorplan Area Optimization; an approach based on Genetic Algorithms is proposed. The method produces optimal results with CPU time requirements comparable with the ones of other approaches but presents some advantages: it is simple to implement, it allows the user to easily trade off CPU time with result accuracy, it requires a limited amount of memory to store partial results, it is not sensible to special structures like nested wheels. Experimental results on the biggest problems proposed in the literature are reported. >

A generic floorplanning methodology

Abstract: One of the important and time consuming stages of design automation is the physical layout design cycle. The physical layout cycle itself consists of several steps, such as partitioning, floorplanning, placement, synthesis, muting and compaction. In this paper, a generic floorplanning methodology is presented. The methodology is based on the hierarchical cooperation of two context-free languages (SCAN and GEOMETRIA). In order to achieve an acceptable planning, the SCAN language defines the partitioning of the floor area and the global acquisition strategy (scan patterns) for the placement of the macro blocks. On the other hand, GEOMETRIA language deals with the local synthesis of the block under the constraints superimposed by global scan patterns. The results obtained by this methodology are very promising in comparison with other floorplanning methodologies. >

Genetic simulated annealing for floorplan design

Abstract: This paper proposes a genetic simulated annealing incorporating characteristics of genetic algorithms into simulated annealing and applies it to a floorplan design of VLSI. The proposed method can effectively search wide state space for an optimal solution using a parallel search starting from many initial points and genetic operators among those paths. Computational experiments show that this method is more powerful to obtain a better solution than the conventional simulated annealing.

Towards modelling a multi-agent knowledge system in engineering design

Abstract: Engineering design projects represent a class of complex synthesis problem. It is characterised by a large solution space and a sequence of decision-making steps at each state in the solution space. An effective solution for such problems depends upon cooperative participation of a number of specialist teams. AI research has been focused in understanding cooperative knowledge systems. The question centre around the complexity of separate knowledge sources in terms of heterarchical and hierarchical organization structure and convergence of design cycle. In this paper, we discuss an approach that employs a set of cooperative knowledge sources involved in design process at various stages of VLSI design, interacting through a common blackboard architecture. A conceptual model based on blackboard architecture is introduced to manage knowledge associated with VLSI design. A case study on the design of VLSI floorplan is considered. The framework enables one to generate, evaluate and come out with alternative design decisions. >

A floorplanning method with topological constraint manipulation

Abstract: In this paper, we propose a heuristic floorplanning method. It is based on tentative insertion of constraints, that intentionally produces redundant constraints to make it possible to search in a wide range of solution space. The proposed method reduces the total area of blocks with the removal and insertion of constraints on the critical path in both horizontal and vertical constraint graphs. Experimental results showed that the quality of solutions of the proposed method is good and even for the large number of blocks, the proposed method keeps a high quality of solution. >

Information analysis in High-level synthesis

Abstract: Author(s): Conradi, Peter | Abstract: This report analyses fundamental design representations that are used in High-Level behavior, register transfer level structure and related floorplan design domains. Different views like structural models, data flow and control representations are described, based on the graphical form of the data description language EXPRESS.It was found that the Design Representation model of the CFI, Inc. can be used to describe both, component nets of structure representations and variable nets of data representations. For the modeling of structured control flow a minimized model has been archived.

Almost linear time optimization for single-row floorplanning

Abstract: Given n cells with their areas and aspect ratio constraints, we present an O(n+d log d) time algorithm to obtain the optimal floorplan of placing these n cells into a single-row, where d is related to the total number of distinct cell classes. Since d is much smaller than n in practical design, our algorithm runs in almost linear time for practical problems.

A new approach to floorplan area optimization: to slice or not to slice?

Abstract: We consider the problem of minimizing the area of a given floorplan by slightly changing its topology and present algorithms for solving it. Our algorithms are very efficient and the results compare favorably with the optimal solutions of the original floorplans. Specifically, we concentrate on converting spiral floorplans into slicing floorplans such that the area is minimized. Naturally, the cyclic channel precedence constraints disappear, which implies that the routing phase will be easier and will require less area. Surprisingly, our experimental results show that in most cases, this conversion is very good with respect to the area of the original spiral floorplan. Namely, the resulting slicing floorplans are smaller than the corresponding spiral floorplans. >

nOHM/spl minus/a multi-process device synthesis tool for lateral DMOS structures

Abstract: This paper presents a synthesis tool that generates layouts of Lateral Doubly-Diffused MOS (LDMOS) structures from electrical parameters of the device or from the current and thermal requirements of the package Optionally, it generates layouts from physical parameters like DMOS width, area and floorplan constraints Multiple layout and metal bus styles are supported Source and drain sense DMOSs used to sample currents of the parent devices can also be generated and automatically placed inside the DMOS The generated layouts are correct by construction The tool has been developed for the Intelligent Power family of integrated circuits from Texas Instruments Inc In this paper the need, capabilities and impact of the tool are presented along with the techniques used to achieve them >

Concurrent placement algorithm and floorplanning based on Occam and the transputer technology

Abstract: In VLSI (very large scale integration), placement is the process of physically placing all electronic functions on a piece of silicon such that minimum wiring and minimum area occupied on silicon are achieved. The paper discusses the feasibility of employing the concurrency and parallel techniques in the placement and floorplanning problem. The hierarchical technique described in the previous work (A. Al Mohanadi, 1989) is carried out sequentially on one processing machine. The placement problem is dealt with sequentially for each level of hierarchy. This technique requires significant CPU time to complete but several placement problems would be solved simultaneously through the use of the parallel processing approach. >

Timing driven floorplanning for general cells

Abstract: The idea of timing driven floorplanning is presented. While optimising the interconnection (wire) delay between cells using the weighted min-cut method, the authors used the nonlinear programming method to reduce both the cell and interconnection delays in the critical paths. Experiments on the examples produced promising results, indicating that the method is effective at optimising the layout phase in VLSI design.

Building Rectangular Floorplans---A Graph Theoretical Approach

Abstract: Rectangular dualisation is a technique used to generate rectangular topologies for use in top-down floorplanning of integrated circuits. In order for this technique to be used in a floorplanning system, its input, the connectivity graph representing an integrated circuit has to fulfill a number of conditions. This paper presents an efficient algorithm that transforms an arbitrary connected graph, representing an integrated circuit, into another graph that is guaranteed to fulfill these conditions and to admit rectangular duals. Effectively, the algorithm solves the global routing problem by using three techniques: passthrough, wiring blocks and collapsed wiring blocks. Resulting floorplans may be passed to a chip assembler and detailed router package to complete the layout. This paper also introduces a novel technique to transform a tree of biconnected sub-graphs into a block neighbourhood graph that is a path.

Area Optimization of Slicing Floorplans in Parallel

Abstract: We first present a parallel algorithm for finding the optimal implementations for the modules of a slicing floorplan that respects a given slicing tree. The algorithm runs in O(n) time and requires O(n) processors, where n is the number of modules. It is based on a new O(n2) sequential algorithm for solving the above problem. We then present a parallel algorithm for finding a set of optimal implementations for a slicing floorplan whose corresponding slicing tree has height O(logn). This algorithm runs in O(n) time using O(logn) processors. Our parallel algorithms do not need shared memory and can be implemented in a distributed system.