Showing papers on "Gate oxide published in 1968"

MOS field effect transistors formed by gate masked ion implantation

Abstract: MOS enhancement mode field effect transistors with a circular geometry and with drains offset from the gate by distances from 0.1 mil to 0.9 mil were implanted with boron ions to fill in the offset region and thus achieve perfect alignment (i.e., no overlap) between gate and drain. The energies used were 50 to 100 keV and a 4000 A-thick aluminum gate acted as a mask to prevent ions from penetrating into the channel region. The best junctions were obtained with 100-keV ions, with the sheet resistances being typically 4000 ω/□ for the implanted region. This additional drain resistance was quite small compared to the channel resistance of the devices and so was not objectionable. Ordinary diffused MOSFET's were included on the same wafers for comparison with the ion implanted MOSFET's. It was found that the differences in noise, leakage, and drain breakdown voltage were not serious. The chief advantage of the ion implanted MOSFET is the extremely low feedback capacitance due to the lack of gate-drain overlap, but this advantage is difficult to exploit in a conventional package because of the package capacitance. However, a significant difference was noted in switching characteristics between diffused and ion implanted MOSFET's mounted on TO-18 headers.

Metal-nitride-oxide-silicon field-effect transistors, with self-aligned gates☆

Abstract: Silicon insulated-gate field-effect transistors (FETs) have been fabricated by processes involving relatively non-critical photoresist and self-limiting etching steps. Important features of the method include the formation of the gate insulator under extremely clean conditions, incorporation of an alkali ion barrier (silicon nitride) to achieve stable device characteristics and automatic alignment of the gate electrode with respect to source and drain. The gate insulator, comprising 600 A of grown silicon dioxide covered with 400 A of silicon nitride, is formed at the beginning of fabrication. Thus, the SiSiO2 interface is established at a point where the best state-of-the-art cleaning techniques can be applied to the starting material. A thick (8000 A) layer of SiO2 is pyrolytically deposited over the nitride to minimize contact capacitances in the finished structure. This must be removed from the active device region, and advantage is taken of the difference in etch rate between SiO2 and silicon nitride to ensure a well-controlled gate insulator thickness. Thus the nitride layer serves the dual function of providing a barrier to mobile ions in the completed structure, and of acting as an etch-resistant layer during fabrication to achieve control over geometry. A polycrystalline layer of silicon is used to form the gate electrode, which is shaped early in the process, and is used to define the limits of the source and drain windows. This aspect of the fabrication assures self-alignment of the gate electrode with respect to source and drain. During the diffusion of source and drain regions the polycrystalline silicon is rendered sufficiently conductive that no metallization of the gate electrode is required, except at one end for contacting purposes. This eliminates the need for a critical photoresist alignment. Both n and p induced-channel (enhancement) devices have been made with this process. Turn-on voltages at 10 μA drain current of +1.35 V (n-channel) and −2.6 V (p-channel) with less than 12 per cent spread over a slice were obtained. Analysis of the device characteristics indicates field-effect mobilities of 335 and 233 cm2/V-sec for the n- and p-channel devices respectively. Aging behavior under bias at 300°C indicates the presence of residual mobile positive charge of the order of 1.5 × 1011 charges/cm2, resulting in turn-on voltage shifts of less than 1 V over several hundred hr with +10 V applied to the gate.

Refractory metal silicon device technology

Abstract: Films 2000–5000 A thick of Mo or W deposited over thin films of thermally grown SiO 2 are shown to be effective high temperature diffusion masks against both phosphorous and boron. These metal films may be precisely patterned and their diffusion masking properties can be used to define the source and drain regions of MOSFETs. In this manner, self-registered MOSFETs can be fabricated with a portion of the diffusion masking metal film acting as the gate electrode. Using P or B doped deposited glasses as diffusion sources, n or p channel enhancement mode MOSFETs were made by diffusion through the exposed thin SiO 2 film into p and n type Si to form source and drain junctions. Contact was subsequently made by etching holes through the oxide layers to the source and drain regions and to the refractory metal gate electrode buried within the oxide layers. These devices exhibit channel mobilities between 200 and 300 cm 2 /V-sec at gate voltages about 10 V above threshold. The stability of MOS structures processed in a similar manner has been measured. After being stressed at ±6 × 10 5 V / cm and 250°C for 15 hr, these devices exhibited shifts in their CV characteristics less than 200 mV.

Radiation Effects in Modified Oxide Insulators in MOS Structures

Abstract: Radiation-induced permanent shifts in gate threshold voltages were measured for MOS structures with variations in the structure of the oxide insulator and compared to the shifts for pure unaltered silicon dioxide. The variations include phosphosilicate glass coating of the oxide surface, aluminum ion-implantation into the surface, and a silicon nitride layer over the oxide. In all cases, the modified form became relatively insensitive to radiation under positive gate voltages and extremely sensitive to radiation under negative gate voltages in contradistinction to the pure oxide, which is much less sensitive at negative than at positive gate voltages. Only the nitride modification led eventually to hardened devices for both polarities. Analysis leads to the conclusion that the models for positive space charge buildup in the oxide must include photoemission of electrons into the oxide from either the silicon or the metal gate, depending on the gate voltage, and also the possibility of mobile holes.

Field effect transistor having passivated gate insulator

Abstract: An insulated-gate field effect transistor is described which includes a gate insulator defined as a laminate structure comprising a phosphosilicate glass (PSG) layer and a silicon dioxide (SiO2) layer, the ratio of the thicknesses of such layers and, also, the P2O5 concentration in the PSG layer being properly chosen to insure stable device characteristics over extended periods under operation conditions.

Dependence of the characteristics of MOS-transistors on the substrate resistivity

Abstract: The d.c. and small-signal a.c. characteristics of MOS-transistors are studied with particular reference to their dependence on the substrate resistivity. Useful approximate expressions are derived for the drain current and for the gate and substrate transconductances. Expressions are also derived for the self and mutual capacitances associated with the gate and the substrate terminals. Apart from increasing the threshold voltage, an increase in the substrate impurity density is found to reduce the saturation drain current and the gate transconductance but to enhance the substrate transconductance. The total transconductance associated with the gate and substrate and the gate transconductance to drain current ratio are, however, shown to be independent of the substrate resistivity. A heavily doped substrate device is thus shown to be superior to a lightly doped substrate device with regard to the total transconductance to drain current ratio. Results of practical measurements on several n -channel MOS-transistors are presented which support the general validity of the theory and the proposed small-signal equivalent circuit. A simple method is suggested for the determination of the substrate control parameter, A , which is related to the substrate impurity density and gate oxide layer capacitance.

Insulated gate field effect transistor used as a voltage-controlled linear resistor

Abstract: The channel resistance of a metal-oxide-semiconductor fieldeffect transistor, or other insulated gate field effect transistor, is linearized by applying to the gate electrode, in addition to the gate voltage for controlling the conductivity, an external feedback voltage having a value of one-half the supply voltage to nullify the effect of the internal feedback due to the supply voltage. In some cases the base electrode is disconnected, but spurious effects caused thereby can be avoided. The voltagecontrolled linear resistor can be employed in DC and AC circuits in applications such as an AC phase shift circuit.

Insulated gate field effect transistor integrated circuits with silicon gates

Abstract: The Silicon Gate Technology is a new approach to fabricating insulated gate field effect transistor circuits, in which the metal gate electrode is replaced by a doped, silicon electrode. The work function difference between the gate electrode and semiconductor bulk will now be determined by the doping of the gate electrode. This leads to normally off p-channel devices with threshold voltages typically between 1.1 v and 2.5 v on material with 1000A gate oxide. It is a self-aligned gate structure and has a buried-gate electrode which allows crossover of gate regions and closer spacing of source-drain contact. The fabrication needs 4 masking steps and was found to be compatible with existing planar technology.

Effect of operating conditions on reverse gate current of junction f.e.t.s

Abstract: With some types of nchannel junction f.e.t.s the measurement of gate leakage current under operating conditions (with a current flowing in the channel) has shown a very much higher value than would be expected from the maker's specification of IGSS. The excess gate current which flows at higher channel voltage is proportional to the drain current and has a small negative temperature coefficient.

Switching and storage characteristics of MIS memory transistors

Abstract: Transistors with memory hawe been constructed in the form of MIS field-effect transistors in which the gate insulator consists of a double layer. Closest to the silicon is a silicon dioxide layer, no more than 15A thick. The importance of this layer will be discussed. It is covered by another layer, which may be silicon nitride, 200-800A thick. Aluminum oxide and silicon dioxide have also been tried as the second layer. At the interface between these two insulator layers, and at an energy level inside the silicon forbidden band, are traps with a density as high as 2×1014cm-2in the form of disorder states. These traps are donor type and may each give off an electron when the silicon is biased positively for a short time with respect to the insulator, turning the transistor ON. When the polarity is reversed the electrons are recaptured by the traps, neutralizing them and turning the transistor OFF. The charge transport is by tunneling.

Controlled rectifier having gate electrode which extends across the gate and cathode layers

Abstract: To permit high rate-of-rise-of-current in a controlled rectifier, the gate electrode extends from the emitter region across the uppermost junction and into contact with the opposite conductivity region under the cathode electrode. When a positive pulse is applied to the gate, the cathode region adjacent the gate is less negatively charged than it would otherwise be if placed conventionally on the P region only. This will reduce current concentration at the emitter edge adjacent to the gate region so that a greater rate-of-rise-of-current is permissible. A groove is interposed between the gate and cathode electrode providing a means of adjusting the impedance between both. This permits limiting of excessive gate-cathode currents through the joining N emitter layer.