Showing papers on "Loopback published in 2011"

Method and system for optical connection validation

Abstract: An optical add/drop multiplexer (OADM) having an Add path for adding optical channel signals input through a plurality of Add ports to an outbound dense wavelength division multiplexed (DWDM) signal, and a Drop path for switching selected channels from an inbound DWDM signal to one or more of a plurality of Drop ports. The OADM has a loopback connection between the Add path and the Drop path. The loopback connection couples a selected loopback channel wavelength from the Add path to the Drop path. The physical connection between a transceiver and the OADM can be verified by connecting the transmitter to an Add port of the OADM and the receiver to a Drop port of the OADM. The OADM is controlled to switch the selected loopback channel wavelength in the Drop path to at least one intended drop port to which the receiver should be connected, and the transmitter is controlled to transmit a predetermined test signal using the loopback channel wavelength. Detecting the test signal by the receiver verifies that the receiver is connected to the at least one intended drop port.

Diagnostic Port for Inter-Switch Link Testing in Electrical, Optical and Remote Loopback Modes

Abstract: A diagnostic testing utility is used to perform single link diagnostics tests including an electrical loopback test, an optical loopback test, a link traffic test, and a link distance measurement test. To perform the diagnostic tests, two ports at each end of a link are identified and then statically configured by a user. The ports will be configured as D_Ports and as such will be isolated from the fabric with no data traffic flowing through them. The ports will then be used to send test frames to perform the diagnostic tests.

Method and system for utilizing low power superspeed inter-chip (LP-SSIC) communications

Abstract: Inter-chip connectivity may be provided in a computing device, which may comprise a USB host and at and at least one USB device embedded within the computing device, based on Universal Serial Bus version 3.0 (USB3.0) interface. In this regard, internal communication of data between the USB host and embedded USB device may be performed via USB3.0 SuperSpeed signals. The USB host and/or the USB3.0 interface may be configured to enable USB3.0 internal communication of data, and to reduce power consumption during the internal communication of data compared to external USB3.0 communications. Configuration of the USB3.0 interface for internal communication of data may comprises modifying and/or adjusting physical (PHY) layer, link layer, and/or protocol layer related parameters, functions, resources, and/or operations. The USB3.0 SuperSpeed signals may be communication using scalable low voltage signaling (SLVS). In this regard, Input/Output (IO) Swing may be set based on loopback training sequence.

Transmission of 10-Gb/s Directly Modulated RSOA Signals in Single-Fiber Loopback WDM PONs

Abstract: We demonstrate the transmission of 10-Gb/s upstream signals over 20-km fiber using a 1.3-GHz-bandwidth reflective semiconductor optical amplifier and a 40-ps delay interferometer (DI) in a loopback configured wavelength-division-multiplexed (WDM) passive optical network. We show that a single DI can be used in a set-and-forget mode to equalize 34 WDM channels anchored at the 100-GHz spaced ITU grid, without any help of postdetection electronic processing.

Buffering and Flow Control in Optical Switches for High Performance Computing

Abstract: We investigate the advantages and disadvantages of different loopback buffer architectures for optical switches and compare their performance via simulation. The simulation results show that, without the use of virtual output queuing, the head-of-line blocking can be alleviated by wavelength parallelism when each separate queue in a loopback buffer has multiple transmitters. Furthermore, the proposed two-level flow control can eliminate packet drop at the switch, resolve rate mismatching due to output queuing at switch outputs, and ensure that congestion occurring at the hotspot port will not affect the performance of non-congested ports.

Method and apparatus for round trip delay kpi monitoring in live network using user plane probe session

Abstract: A method and apparatus for Round Trip Delay KPI Monitoring in a live network using a user plane probe session is disclosed for measuring round trip delays in a manner that allows latency to be apportioned to network elements. The method and apparatus for Round Trip Delay KPI Monitoring in a live network using a user plane probe session includes transmitting a loopback packet containing a probe session indicator and capturing timestamps of arrival and departure times at each network element traversed by the loopback packet, and then transmitting the timestamps to a Network Management System.

Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits

Abstract: Accurate measurement of aperture jitter for high-speed data converters is a difficult problem, since aperture jitter should be precisely separated from other jitter components as well as additive noise. This problem results in low test accuracy and high-yield loss. This paper presents a novel methodology for accurately predicting aperture jitter using a cost-effective loopback methodology. By using an efficient spectral loopback scheme, aperture jitter is precisely separated from input jitter and clock jitter as well as additive noise present in the DUT. Hardware measurement results show that this approach can be effectively used to predict the aperture jitter of a DUT, with an 89% reduction in the prediction error compared with previous approaches.

Systems and methods for data write loopback based timing control

Abstract: Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted loopback circuit is discussed that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The read circuit is operable to sense data from a storage medium, and to provide the sensed data as a read output. The magnetic write circuit is operable to provide a write output corresponding to an excitation signal of a write head. The heat write circuit is operable to provide a heat output corresponding to an excitation signal of a heat source. The loopback circuit is operable to selectively couple a derivative of the heat output to the read output and to selectively couple a derivative of the write output to the read output.

Wire order test method

Abstract: The invention discloses a wire order test method for testing cable wire order. The method is as follows: a first N-path analog quantity switch selector is placed at the side of a cable to be tested, and a far-end loopback line is arranged; the far-end loopback line is respectively connected with resistors R1-RN in series, and the requirement of selecting far-end loopback resistors is that the sumof any two resistors is not equal; local 5 V high level is output through the line and then delivered to a far-end loopback passive joint; the 5 V high level is looped back to the local through the tandem resistors in the line and then through the tandem resistors on the other line; and because the sum of any two far-end resistors is not equal, the partial pressure value on any loopback line is not equal, thus the connection manner of the wire order can be judged. In the invention, a single port device is used to achieve measurement and the cost of the test device can be saved. By using the method, the measurement of any wire order can be realized. The method can be used in more occasions owing to the any wire order judgment function.

Method and system for adjusting transmission power

Abstract: A system and method for measuring transmission power distortion in a wireless communication device are disclosed. In one embodiment, the method comprises reading an operating temperature of the wireless communication device and enabling a loopback path between a transmission circuit and a receiver circuit of the wireless communication device. Using the loopback path, the wireless communication device can calibrate the transmission power output by storing data for compensating the distortion of the transmission power. The data can be stored in a calibration look up table for use by the wireless communication device.

System and method for calibration of serial links using a serial-to-parallel loopback

Abstract: A system and method for calibration of serial links using serial-to-parallel loopback. Embodiments of the present invention are operable for calibrating serial links using parallel links thereby reducing the number of links that need calibration. The method includes sending serialized data over a serial interface and receiving parallel data via a parallel interface. The serialized data is looped back via the parallel interface. The method further includes comparing the parallel data and the serialized data for a match thereof and calibrating the serial interface by adjusting the sending of the serialized data until the comparing detects the match. The adjusting of the sending is operable to calibrate the sending of the serialized data over the serial interface.

2g, 2.5g rf loopback arrangement for mobile device self-testing

Abstract: In a mobile communication device a loopback technique is used to enable the receive chain circuitry and digital baseband block to perform self tests on the transmit chain circuitry of the same mobile communication device for 2G and 2.5G operating Bands and channels. A transmit chain circuit is set to transmit a selected receive Band channel, which is attenuated via a loopback path within the mobile communication device's front end module and, in some embodiments, via a leakage signal path between adjacent or proximate LNA inputs of separate receive chain circuits.

Apparatus and methods for controlled error injection

Abstract: In accordance with an embodiment of the invention, precision control of error injection may be accomplished by way of synchronous error signals accompanying data transfers along various pipeline stages of a data path. The synchronous error signals may be used to trigger error events in a given protocol logic block (i.e. in a given sub-component of the data path). The protocol logic block is configurable to determine whether any action is to be taken upon the assertion of the error signal. Multiple error events may be triggered as the data signal (and its accompanying synchronous error signal) passes through pipelined functions of the data path so as to create complex error conditions. In addition, deterministic handling of created errors may be accomplished using a loopback path with bypassable blocks on both forward and reverse transformations. Other embodiments, aspects and features are also disclosed.

Wideband Low-Reflection Transmission Lines for Bare Chip on Multilayer PCB

Abstract: In recent years the interest in the design of low cost multistandard mobile devices has gone from technical aspiration to the commercial reality. Usually, the emerging wireless applications prompt the conception of new wireless standards. The end user wants to access voice, data, and streaming media using a single wireless terminal. In RF perspective, these standards differ in frequency band, sensitivity, data rate, bandwidth, and modulation type. Therefore, a flexible multistandard radio receiver covering most of the cellular, WLAN, and short range communication standards in 800MHz to 6GHz band is highly desired. To keep the cost low, high level of integration becomes a necessity for the multistandard flexible radio. Due to aggressive CMOS scaling the fT of the transistors has surpassed the value of 200 GHz. Moreover, as the CMOS technology has proven to be the best suited for monolithic integration, therefore it seems to be the future choice for the physical implementation of such a flexible receiver. In this thesis, two multiband sampling radio receiver front-ends implemented in 130 nm and 90 nm CMOS including test circuitry (DfT) are presented that is one step ahead in this direction. In modern radio transceivers the estimated cost of testing is a significant portion of manufacturing cost and is escalating with every new generation of RF chips. In order to reduce the test cost it is important to identify the faulty circuits very early in the design flow, even before packaging. In this thesis, on-chip testing techniques to reduce the test time and cost are presented. For integrated RF transceivers the chip reconfiguration by loopback setup can be used. Variants including the bypassing technique to improve testability and to enable on-chip test when the direct loopback is not feasible are presented. A technique for boosting the testability by the elevated symbol error rate test (SER) is also presented. It achieves better sensitivity and shorter test time compared to the standard SER test. Practical DfT implementation is addressed by circuit level design of various test blocks such as a linear attenuator, stimulus generator, and RF detectors embedded in RF chips without notable performance penalty. The down side of CMOS scaling is the increase in parameter variability due to process variations and mismatch. Both the test circuitry (DfT) and the circuit under test (CUT) are affected by these variations. A new calibration scheme for the test circuitry to compensate this effect is presented. On-chip DC measurements supported by a statistical regression method are used for this purpose. Wideband low-reflection PCB transmission lines are needed to enable the functional RF testing using external signal generators for RF chips directly bonded on the PCB. Due to extremely small chip dimensions it is not possible to layout the transmission line without width discontinuity. A step change in the substrate thickness is utilized to cancel this effect thus resulting in the low-reflection transmission line. In summary, all of these techniques at the system and circuit level pave a way to new opportunities towards low-cost transceiver testing, especially in volume production.

Voice channel detection method and base station controller

Abstract: The invention provides a voice channel detection method and a corresponding base station controller. In the invention, the base station controller starts a detection point with digital signal processing capability to conduct loopback detection according to a loopback point with timeslot cross-linking capability in a loopback timeslot, and whether a voice channel with end points as the detection point and the loopback point goes wrong or not is judged according to the result of loopback detection returned by the detection point. According to the invention, the method that the detection point is started to conduct loopback detection according to the loopback point in the loopback timeslot is adopted, so that whether the voice channel with the end points as the detection point and the loopback point goes wrong or not can be distinguished.

MPLS Transport Profile Lock Instruct and Loopback Functions

Abstract: This document specifies one function and describes a second function which are applicable to MPLS transport networks. The first function enables an operator to lock a transport path while the second enables an operator to set, in loopback, a given node along a transport path. This document also defines the extension to MPLS operation, administration, and maintenance (OAM) to perform the lock function.

Node device, integrated circuit and control method in ring transmission system

Abstract: A node device in a ring transmission system in which a plurality of node devices are connected as a ring via serial links has a PHY transitioning between a normal mode and a loopback mode with timing that maintains symbol lock between an idle frame transmitted to a later serial link in the normal mode according a transmission instruction, and an idle frame from an earlier node device looped back for output to a later serial link during the loopback mode, thus performing relay processing on non-locally addressed data packets during the loopback mode.

Link detection method, system and loopback initiation equipment

Abstract: The embodiment of the invention relates to a link detection method, a link detection system and loopback initiation equipment. The link detection method comprises the following steps of: receiving a testing message from a testing message transmitter, and transmitting the testing message to a loopback responder by using a loopback initiator, wherein the loopback initiator is set to allow loopback forwarding in advance; receiving the testing message looped back by the loopback responder; and transmitting the testing message looped back by the loopback responder to the testing message transmitter, so that the testing message transmitter can determine whether a link between the testing message transmitter and the loopback responder is normal or not. In the embodiment of the invention, the loopback initiator is configured to allow the loopback forwarding in advance, and the testing message looped back by the loopback responder can be transmitted to the testing message transmitter, so that the testing message transmitter can determine whether the link between the testing message transmitter and the loopback responder is normal or not according to whether the testing message is received normally or not to realize end-to-end link detection.

Loopback testing with phase alignment of a sampling clock at a test receiver apparatus

Abstract: Methods and test receiver apparatus are provided for loopback testing of a unidirectional physical layer device. The disclosed methods and test receiver apparatus allow for the phase of a sampling clock implemented at the test receiver apparatus to be aligned with the phase of a test data signal.

Service link tracking realization method and device

Abstract: The invention provides a service link tracking realization method and a service link tracking realization device, which are applied to a multi-protocol label switching-transport profile (MPLS-TP) network The method comprises the following steps of: detecting the amount N of transmitting node equipment between a first maintenance end point and a second maintenance end point when a message is transmitted from the first maintenance end point to the second maintenance end point; transmitting a first loopback request message to the second maintenance end point, wherein the set time to live of the first loopback request message corresponds to time required by the transmission of the first loopback request message to the Mth node equipment, and M is less than or equal to N; and receiving a first loopback response message in response to the first loopback request message from the Mth node equipment, and reporting link information between the first maintenance end point and the Mth node equipment By the method and the device, actual service traffic conditions between a source-end maintenance end point (MEP) and a destination-end MEP can be completely acquired, and the function of performing link tracking on a point-to-point co-routing bidirectional path in the MPLS-TP network is realized

Transformer-Coupled Loopback Test for Differential Mixed-Signal Dynamic Specifications

Abstract: Loopback tests for a differential mixed-signal device under test (DUT) have rarely been attempted since any imbalance introduced by design-for-test (DfT) circuitry on differential signaling delivers an imperfect sinusoidal wave to the DUT input or output, thereby degrading the DUT performance. In addition, this methodology inherently suffers from fault masking. These problems trigger low test accuracy and serious yield loss. This paper presents a novel methodology for the efficient prediction of individual DUT dynamic performance parameters with a radio-frequency (RF) transformer in loopback mode to overcome the imbalance of DfT circuitry and the fault masking. Cascaded RF transformers with different multiplicative weights are selected in three combinations by a multiplexer to create three separate loopback responses. These responses are used to characterize the DUT dynamic performance. Hardware measurement results show that this approach can be effectively used to predict the specifications of a DUT.

Core-driven translation and loopback test

Abstract: A translation and loopback test for input/output ports is described. In one example, a method includes receiving a test packet on an output of a high speed processor link, looping the test packet back to an input of the high speed processor link, and detecting the receipt of the looped back test packet to test operation of the high speed link.

Method and apparatus for circuit emulation with integrated network diagnostics and reduced form factor in large public communication networks

Abstract: An multiservice access device (MAD) for Ethernet and DS1/DS3 services is provided for public communications carriers (telcos), for example, and has a reduced form factor (e.g., Type 400 NCTE mechanics or small enclosure), at least two 2.5 Gb/1 Gb facility side ports, at least four full rate GigE drops, complementary RJ48C demarcation and stub-ended DS1 cable options, integral T1 NIUs for in-band loopback, NPRM, SPRM, AIS/AIS-CI and RAI/RAI-CI diagnostics, lightning protection, and protection switching. The MAD has built-in SynchE and IEEE 1588 synchronization, and Stratum 3 and incoming DS1/DS3 synchronization capabilities.

Technique for providing loopback testing with single stage equalizer

Abstract: Devices and methods for serial loopback testing in an integrated circuit (IC) are provided. To implement loopback testing, an equalizer stage of a receiver of the IC is powered down. In addition, the common-mode voltage of the equalizer stage is reduced and/or a bulk node of the equalizer stage is connected to ground. Doing so may reduce the impact of capacitive coupling from the input pins of buffer, thereby improving the quality of the loopback output signal.

Optical network unit and port loopback detection method thereof

Abstract: The invention discloses an optical network unit and a port loopback detection method thereof. The method comprises the following steps that: an ONU (Optical Network Unit) receives a management entity (ME) field of an OLT (Optical Line Terminal), wherein one or more reserved numbers in the desired type of the ME field express to need port loopback detection by the ONU; and the ONU carries out the port loopback detection according to the ME field. The invention solves the problems that the realization ways of port loopback detection of the ONU are not uniform and butting and interworking detection is difficult to be carried out, provides convenience for each manufacturer to rapidly realize a port loopback detection function, reduces the workload and increases the efficiency of butting and interworking detection.

Transmitter only ic chip having external loopback test function and therefore external loopback test method

Abstract: PURPOSE: A transmitting integrated circuit with an external loopback test function and an external loopback test method according to the same are provided to reduce cost required for the external loopback test. CONSTITUTION: Drivers are loaded on a transmitting integrated circuit and transmit data through transmitting pads which are installed to be corresponded with a plurality of channels. A loopback test circuit(100) receives data through one of transmitting pads as external loopback data. The data is transmitted through one of remained transmitting pads. The received external loopback data is compared with original transmitting data.

Multi-function multi-GHz ATE extension using state-of-the-art FPGAs

Abstract: This paper presents a multi-function multi-GHz test module designed to enhance the performance capabilities of automatic test equipment (ATE). The test module is designed with a core logic block consisting of a high-performance FPGA. It also contains an application specific logic block that is designed to perform multiple functions not possible with the FPGA alone. We demonstrate five applications: high-speed signal multiplexing up to 16Gbps, loopback testing, jitter injection, amplitude adjustment, and timing adjustment. The loopback path allows testing up to 9.28Gbps. Digital timing adjustment up to 10ns in 10ps increments, and fine adjustment up to 61ps is shown. Jitter injection up to 81ps (p-p) and amplitude adjustment over a range of 600mV are demonstrated. The core logic block itself has capabilities to generate 10Gbps output signals with 38ps (p-p, BER = 2×10−5) jitter. The test module is designed to be compatible with existing ATE infrastructure; connecting to the device under test (DUT) via a device interface board (DIB). A bypass option allows signals from the ATE to pass through to the DUT, permitting use of traditional ATE functions.

Data communication apparatus and method of controlling the same

Abstract: In a data communication apparatus which communicates with another data communication apparatus via a network, and a method of controlling the same, an address book in which a plurality of addresses used to send data are registered is published to other data communication apparatus via the network, and in a case that a loopback address is included in the plurality of addresses registered in that address book, the other data communication apparatus is restricted from accessing the address book including the loopback address.

Shortcut protection method based on path-bound MPLS-TP (Multi-Protocol Label Switching-Transmission Protocol)

Abstract: The invention discloses a shortcut protection method based on a path-bound MPLS-TP (Multi-Protocol Label Switching-Transmission Protocol), comprising the following steps of: configuring a ring network protection link: configuring a protection path for loopback protection and a Steering-protected path for an LSP (Logical Signal Processor) of an upper ring by a ring network node; and when the ring network generates faults, carrying out the processing steps of: (1) processing adjacent nodes of a fault link; and (2) processing adjacent nodes of a non-fault link. The invention can find the protocol support without topology and simultaneously improve the Steering protection speed, which has great significance on improving the performance of the ring network based on the MPLS-TP technology.

Loopback output router for reliable Network on Chip

Abstract: We present a new reliable high-performance interconnection approach destined for complex System on Chip based on the network-centric approach. The originality of our approach is to avoid the lost of data packets, detect routing errors and reduce data packets latency by emptying output buffer when the neighbour router is unavailable. We present the basic concepts of the reliability communication technique and FPGA implementations.