Showing papers on "Master clock published in 1999"

Apparatus and method for synchronizing an scdma upstream or any other type upstream to an mcns downstream or any other type downstream with a different clock rate than the upstream

Abstract: A bidirectional digital data communication system which generate phase coherent upstream clock and carrier signals from recovered downstream clock generated from a master clock in a central unit. The preferred species uses any downstream clock rate and generates a phase coherent upstream clock so long as the two clock rates can be related by the ratio M/N where M and N are integers. One embodiment uses an MCNS downstream and an SCDMA upstream and uses MNCN timestamp messages in the downstream to achieve an estimate of RU frame offset prior to establishing frame alignment using a ranging process. The use of timestamp messages to estimate the offset is aided by a low jitter method for inserting timestamp messages by avoiding straddling of MPEG packet headers with the sync message. Clock slip is detected by counting upstream clock cycles over a predetermined downstream clock interval and the RU transmitter is shut down if slip is detected to prevent ISI interference from misaligned codes. An SCDMA transmitter for the minislot environment of 802.14 and MCNS is disclosed along with a receiver for the minislot environment using TDMA or SCDMA demultiplexing.

System and method for dynamic clock generation

Abstract: An application specific integrated circuit (ASIC) has a clock controller that dynamically selects an appropriate clock frequency for a resource. The ASIC includes a central processing unit (CPU), on-chip memory, a memory controller controlling external memory devices, a system bus, and various peripheral controllers. Devices that can be accessed by other devices, such as the on-chip memory, the memory controller, and the system bus are “resources.” The devices that access the resources are “controllers.” The ASIC generates a master clock and the clock controller derives clocks for driving the resources and controllers from the master clock. A multiplexer (MUX) in the clock controller selects the clock that is passed to a resource. Each controller has a request line to the clock controller for signaling when the controller is accessing a resource. The clock controller has a programmable register for each controller holding a value representing the bandwidth utilization of the controller and an adder and a frequency table. The adder sums the contents of the bandwidth registers of the controllers that are accessing a resource. The sum is an index to an entry in a frequency table. The value held in the frequency table is applied to the selection inputs of the MUX to select the clock for the resource. If no controllers are requesting access to the memory controller, the clock controller shuts down the memory clock. Accordingly, the clock frequency of the resource is determined by the bandwidth utilization of the controllers requesting access to the resource.

Organization of time synchronization in a distributed system

Abstract: A distributed system with mechanisms for automatic selection of master and slave clocks to be used for clock synchronization. The distributed system includes a set of nodes (20-24), including a first node and a second node, each having a local clock (30-34) and a set of information (40-44) pertaining to the local clock (30-34). The first node transfers a packet (50) on a communication link (12) that carries the information (52). The second node receives the packet (50) on the communication link (12) and determines whether the local clock of the second node is a master clock that synchronizes a time value in the local clock of the first node or a slave clock that synchronizes to a time value from the local clock in the first node by comparing the information (52)in the packet (50)to the information pertaining to the local clock in the second node. Automatic selection of master and slave clocks in boundary nodes (92) is provided along with mechanisms for determining clock synchronization delays and mechanisms for reporting jitter associated with communication devices (14).

A high speed, 500 frames/s, 1024/spl times/1024 CMOS active pixel sensor

Abstract: The paper presents a high-speed (500 f/s) large-format 1 K/spl times/1 K 8 bit 3.3 V CMOS active pixel sensor (APS) with 1024 ADCs integrated on chip. The sensor achieves an extremely high output data rate of over 500 Mbytes per second and a low power dissipation of 350 mW at the 66 MHz master clock rate. Principal architecture and circuit solutions allowing such a high throughput are discussed along with preliminary results of the chip characterization.

Baseband receiver apparatus and method

Abstract: A base band receiver apparatus comprising an RF front end section, a pulse detection unit wherein modulated, ultra-short spread spectrum pulses are detected, and a data recovery unit wherein clock and data recovery from the detected pulses are carried out. The RF front end includes an antenna and circuitry for filtering and amplifying RF signals received by the antenna. The pulse detection unit preferably includes a tunnel diode or Schottky diode which rectifies the incoming voltage signals from the RF front end and provides a power envelope, a high pass filter which removes residual DC offset from the voltage signals, and a comparator which provides threshold voltage detection. The data unit includes a clock recovery function for generating master clock timing information from the detected pulse stream, a phase offset detector for determining delays associated with pulsed data transmission from other non-master networked devices, and a data recovery function for determining digital values for incoming signals according to timing information from the clock recovery function and phase offset information from the phase offset detector.

Optimal and efficient clock synchronization under drifting clocks

Abstract: We consider the classical problem of clock synchronization in distributed systems. Previously, this problem was solved optimally and efficiently only in the case when all individual clocks are non-drifting, i.e., only for systems where all clocks advance at the rate of real time. In this paper, we present a new algorithm for systems with drifting clocks, which is the first optimal algorithm to solve the problem efficiently: clock drift bounds and message latency bounds may be arbitrary; the computational complexity depends on the communication pattern of the system in a way which is bounded by a polynomial in the network size for most systems. More specifically, the complexity is polynomial in the maximal number of messages known to be sent but not received, the relative system speed, and time-stamp size. Our result has two consequences. From the theoretical standpoint, it refines the known bounds for optimal synchronization. But even more importantly, it enables us to derive new optimal algorithms that are reasonably efficient for most practical systems.

Circuits and methods for controlling timing and slope compensation in switching regulators

Abstract: Circuits and methods for controlling timing and slope compensation in switching regulators are provided. These circuits and methods include a timing control circuit that controls the timing of the switching of one or more switching regulator output stages so that the switching occurs at evenly spaced time intervals, and a slope compensation circuit that produces a slope compensation signal having a waveform that need not match the waveform of any oscillator signal, nor that need have the same period as the oscillator signal. Timing control is performed by dividing a master clock signal using a T flip-flop and a “rolling clock” (or “Johnson counter”) to produce 2N clock phase signals. Slope compensation is provided by generating a slope compensation signal using decoding logic, a digital-to-analog converter (DAC), and an integrator.

Fast re-synchronization of independent domain clocks after powerdown to enable fast system start-up

Abstract: A system having several clock domains must have domain clocks properly aligned before powering up from a low-power or power-down mode. The domain clocks can be quickly aligned to enable fast system start-up if the clocks are forced into a rough alignment before a fine alignment process begins. Initially, a phase offset between the domain clocks is determined using a sync pulse, which indicates a location of one of the domain clocks relative to the other domain clock. Next, the domain clocks are forced into a minimum phase offset configuration by phase stalling one of the domain clocks. The phase stalling includes adjusting the pulse width of one of the domain clocks to force the clock into a rough alignment with the other domain clock. Finally, the domain clocks are fine aligned, and the system is placed into a normal power mode.

Computer system including multiple clock sources and failover switching

Abstract: A system and method for providing redundant, synchronized clocks in a computer system. Upon a failure of a master clock signal, the system switches over to a slave clock signal synchronized with the master clock signal. Switching logic is coupled to receive a first clock signal and a second clock signal. The switching logic selects either the first clock signal or the second clock signal as a local clock signal. The switching logic further monitors the first clock signal for a failure. If a failure is monitored, the switching logic accepts the second clock signal as the local clock signal in place of the first clock signal. One or more clock local loads operate according to the local clock signal. The switching logic may control the input to a phase locked loop (PLL) that provides the local clock signal to the local clock loads. The method includes a PLL synchronizing an output clock signal with the master clock signal. The output clock signal is used by at least one local clock load for timing. The switching logic monitors the master clock signal and the slave clock signal for a failure. Upon a failure of either the master clock signal or the slave clock signal, the switching logic notifies a system controller of the failure. Upon the failure of the first clock signal, the switching logic switches the second clock signal in place of the first clock signal as the master clock signal for the PLL, causes the second clock signal to fail-over and to take over as the master clock source to the PLL, and causes the second clock source to provide a reference control signal to the second clock source. Clock switching is automatic and does not interrupt or interfere with operation of the computer system.

Synchronizing data between differing clock domains

Abstract: A processor-based system provides communication among multiple computer devices operating at different frequencies utilizing clock synchronization. Phase relationship is maintained between clock signals running a different frequencies such that a read cycle of a device operated at the faster frequency is initiated when the clock signals are in phase. A write cycle of the faster frequency device is initiated when the clock signals are out of phase. A synchronization signal is generated by sampling the clock signals together to indicate the phase relationship. In addition, a return clock, derived from the faster clock, drives external devices. Information sent from internal devices to external devices are passed through a register driven by the return clock. Timing delays for information presented to the external devices is avoided as the register transmits all information according to the return clock. Return data is clocked into a return register also according to the return clock. The return register presents the return data at the next read cycle according to the slower clock signal.

Master-slave synchronization

Abstract: The invention relates to synchronization of network elements in a network that uses master-slave synchronization. The use of the known monitoring bit MCB (Master Clock Bit) is expanded in the method so that it is transmitted all the way from the master network element, for example the mobile switching center (MSC). If one of the network elements located between the master network element and a specific slave network element, for example a base station, does not accept the received signal as the synchronization source because of its quality, the network element in question forces the MCB bit located in the signal that the element transmits further to state 1. If the transmission unit of a specific slave network element is locked to the signal which includes the MCB in state 1, or if the element is forced to revert to using the internal clock because of a fault situation of the signal, the transmission unit activates the alert. Before the start of and during the synchronization of the base station clock, the fault status is read from the transmission unit and the synchronization is prevented or interrupted if the alert is on. The alert is given to other units of the base station in question from which the fault monitoring unit further transmits it through a separate operations and maintenance network to the operations center of the network operator.

Multinode computer system with distributed clock synchronization system

Abstract: A multinode multiprocessor computer system with distributed local clocks wherein a local clock may be synchronized with other clocks in the system without affecting the operation of the other clocks. A local clock to be synchronized is reset and counts an elapsed time since the reset. Simultaneously with resetting the local clock, a clock value from a clock on a source node is stored. The clock value from the source node is copied to the node to be synchronized and added to the elapsed time. The resulting summation is then stored in the local clock to be synchronized. As a result, the local clock is synchronized to the clock on the source node. In one system embodiment, the local clock includes a dynamic register and a base register and an adder adds the two portions together to generate an output of the local clock. For a node being synchronized, the dynamic portion is reset and allowed to count the elapsed time while the base portion is loaded with a clock value copied from the source node. In another system embodiment, a clock register stores both dynamic and base portions. For a node being synchronized, the clock register is reset and allowed to count the elapsed time. The base portion from the source node is then added to the clock register and stored in the clock register.

Method of providing clock signals to load circuits in an ASIC device

Abstract: An ASIC device and method provide clock signals to load circuits having a balanced clock tree including a master clock line, for example a clock trunk or H-tree, and branched clock lines feeding the clock signals to load circuits and being balanced with respect to the delays and loads in domains of the ASIC device to which the branched clock lines supply the clock signals. The ASIC device and method generate derived clock signals by gating the master clock signal, in which the derived clock signals have a frequency reduced by a factor n>1 (n=2, . . . , N), which is adapted to the need of the load circuits in a particular domain, and route the master clock signal and/or the derived clock signal for a particular domain to the load circuit of said domain.

Circuit and method for generating a write precompensation signal

Abstract: A circuit that generates a write precompensation delay signal includes a precoder, a delayed clock pulse selector, a delayed clock pulse generator, and a non-return-to-zero (NRZ) modulator. A master clock signal and serialized data operating at the master clock rate are inputs to the precoder which generates a precoded data signal operating at the master clock rate. The delayed clock pulse selector generates clock pulse selection signals based on the precoded data. The delayed clock pulse generator generates at least two delayed clock signals, selects either none or one of the delayed clock signals according to the clock pulse selection signals, and generates a return-to-zero (RZ) signal whose time periods comprise either a zero if no delayed clock signal is selected or a pulse of the selected delayed clock signal. The NRZ modulator generates the precompensation signal from the RZ signal, and the precompensation signal has a maximum precompensation delay of at least 50% of the master clock time period. Preferably, the precompensation circuit also includes a ramp waveform and threshold voltage generator to generate at least one ramp waveform and at least two threshold voltages. A preferred embodiment of the invention includes time-interleaving the precoded data into odd and even data sequences each operating at half the master clock rate. In this case, the ramp waveform and threshold voltage generator preferably generates an odd and an even waveform.

Method of identifying location using a master clock to synchronize time of arrival signals

Abstract: A method is provided of identifying position location of a transmitter device, such as a mobile or portable, in an inbound system The inbound system includes free receivers all coupled, over appropriate radio frequency (RF) links, to a common reference receiver, the latter equipped with a high precision timebase master clock for receiver synchronization purposes Rather than requiring each and every receiver to maintain a separate high-precision timebase to record position related timing signals for position location determination, in accordance with a preferred embodiment, the free receivers are configured to detect timing signals from the transmitter device, and without timestamping them, quickly forward them (in the form of a signal-received indication) after a fixed or otherwise known time delay to the reference receiver The reference receiver, in turn, timestamps all signals from all free receivers according to its own master clock high precision timebase In this way, it is possible to synchronize the forwarded signal-received indications to the reference receiver master clock and to use the results to derive useful position location information This is achieved without equipping high precision timebase clocks in the free receivers, which in most instances is prohibitively expensive

Chopper-stabilized amplifier with digital frequency modulated clocking and method

Abstract: The chopping frequency driving a chopper-stabilized amplifier (CSA) is dynamically varied between an upper and lower frequency limit to reduce the intermodulation distortion, clock noise and low-frequency noise found in prior art designs. The upper limit is set to accommodate the settling times required by the CSA's memory capacitors, and the lower limit is set to a non-zero frequency significantly greater than DC to reduce low frequency noise. The two limits permit IMD and clock noise to be widely scattered and enable a near optimum trade off between IMD and chopping noise on one hand, and low frequency noise on the other. The chopping frequency is preferably generated digitally with a loadable counter which divides down a fixed frequency master clock, with the binary value presented at the counter's load inputs periodically varied to dynamically vary the division ratio and thus frequency modulate the chopping frequency. The binary value presented to the load inputs are generated with a second counter or a PRBS, for example, which establish the upper and lower frequency limits.

New Steering Strategies for the USNO Master Clocks

Abstract: : All U.S. Naval Observatory (USNO) steering situations involve compromises to minimize the degradation of short-term stability of a steered clock while gaining maximal benefits from the long-term stability of the reference. In the case of steering UTC(USNO) to UTC, extra complications arise due to the 30-day data interval and the 15-day delay associated with the transfer of new information. A technique that minimizes the amount of control required to steer the USNO mean to UTC will be presented. Different strategies designed for optimal steering of UTC(USNO) and a backup master clock system located at the USNO will be described. Some of these strategies involve steering a maser to an intermediate mean that is steered to an extrapolation of UTC. Examples of optimal steering on real data will be reported.

Low deviation synchronization clock

Abstract: A local clock used for synchronizing events in an industrial control system may be synchronized with a master clock according to synchronization signals received at a first period. Updating of the local clock is performed on a more frequent basis than the receipt of the update signals. By using the update signals to derive an error value which is incrementally applied to the clock at a much higher rate, the maximum deviation is reduced. The system works with clocks having discrete frequency outputs by adjusting the update rate so as to effectively produce a continuously variable output frequency for the local clock over an interval equal to the update rate.

Timing recovery system for a 10 BASE-T/100 BASE-T ethernet physical layer line interface

Abstract: A phase lock loop is provided for recovering timing information from a received data signal in a 100Base-TX receiver. The phase lock loop includes a phase encoder ( 803 ) for generating a reference phase error. An output phase value on a bus ( 809 ) is subtracted from the reference phase value on line ( 805 ) with a subtraction block ( 813 ) to generate a phase error. This phase error is averaged and decimated over a predetermined number of potential symbol transitions in the received signal. The output phase error is provided from a block ( 815 ) on a line ( 817 ) to a loop filter. This output is provided only once for each decimation operation such that the loop filter can operate at a lower clock rate. The phase error output is then utilized to select one of multiple clocks that correspond to the phase error, these being incremental phase clocks referenced to a master clock. This utilizes a clock multiplexer ( 1427 ) to select one of the multiple clock inputs which are delayed in phase off of the master clock. This selection is synchronized with the receive clock output of the multiplexer ( 1427 ) with the original output phase converted to gray encoded values. The ensures that only a single bit will be changed for any phase change such that only a single bit error will occur corresponding to a single value error.

Automatic clock switching

Abstract: A clock switch controller has a clock status register which stores current clock data which identifies which of two or more clock signal sources is a current clock signal source currently in use as a system clock signal source. State machine logic of the controller automatically switches, in response to a clock switch signal, the system clock signal source from the current clock signal source to a new clock signal source of the two or more clock signal sources.

On-board clock-control templates for testing integrated circuits

Abstract: An integrated circuit employing a built-in self testing is provided. The circuit comprises a clock controller, a plurality of logic domains, and a system clock. The clock controller includes a plurality of programmable clock templates. The logic domains operate based on clocks having different clocks and/or on different edges of the clocks and operable asynchronously with respect to the others of said logic domains. The system clock is distributed to the logic domains and to the clock controller. Herein, each logic domain generates master/slave signals in response to the received system clock and each of the clock templates distributes enabling signals to at least one corresponding logic domain. The enabling signals are for selectively gating the generated master/slave signals for distribution throughout at least one corresponding logic domain.

Method and apparatus for altering timing relationships of non-overlapping clock signals in a microprocessor

Abstract: A clock generation circuit 122 with a selectable non-overlap time period is described for use on an integrated circuit. A master clock signal M which has a latching edge is formed in response to a reference clock signal fclk. A slave clock signal S which has a driving edge is also formed in response to the reference clock signal. The driving edge of slave clock S is delayed by a non-overlap feedback path 504 so that the driving edge is delayed by the non-overlap time period after the latching edge of master clock M. The value of the non-overlap time period is selected by switching delay circuitry 531 in or out of the non-overlap feedback path on signal line 504 . A control signal STRSTST is set high or low to select the value of the non-overlap time period. A sense circuit 561 or a scan latch 562 also can select the non-overlap time period.

Clock management method and transmission apparatus for synchronous network system

Abstract: In a clock management apparatus for a synchronous network system, when the quality of a clock signal is deteriorated, the clock signal is switched to another clock signal automatically to continue synchronous communication. Clock signals are received and extracted by transmission/receiving units of the synchronous network system. A plurality of clock signals including the extracted clock signals and a clock signal from an external clock are selectively switched by a clock switching unit, and a master clock signal is selected and output based on quality information transferred with each clock signal. The master clock signal is applied to a clock generator generate a clock signal. A quality control table is used to convert quality information into associated quality levels. A quality determination processing unit issues an alarm when the quality level of the master clock signal is deteriorated beyond a threshold provided by a synchronization management table.

Generating a clock signal

Abstract: An apparatus which generates a clock signal includes a first phase mixer which generates an initial clock signal based on a first set of reference clocks and a buffer which adds a first predetermined delay to the initial clock signal to produce a first clock signal. A phase detection circuit detects a difference in phase between the first clock signal and a master clock signal, and a control circuit selects a second set of reference clocks based on the difference in phase and a second predetermined delay. A second phase mixer generates an output clock signal based on the second set of reference clocks.

Low power glitch-free clock switch

Abstract: A glitch-free clock switch circuit for an integrated circuit having a plurality of asynchronous clocks, wherein only one clock is selected at a time, and wherein the clock switching circuitry for switching from a currently selected clock to an inactive clock to next be selected is activated only for the time it takes to complete the switching. The clock switch circuit includes at least three sets of clock drivers, wherein each set is comprised of two drivers and separate clock drivers are each associated with the output clock, the currently selected clock and the clock to next be selected, respectively. An edge detector turns on these clock drivers in response to a clock select signal, and a set of synchronizers receive and synchronize the clock select signal first with the output clock and then with the currently selected clock and the clock to next be selected, respectively. A plurality of logic gates switches the clock output from the selected clock to the clock to next be selected by the clock select signal. A reset circuit turns off the clock drivers once the clock output has been switched from the selected clock to the clock to next be selected. The clock drivers for clocks that are not selected are turned off during and after the period of time the selected clock is switched to the clock to next be selected. Once the switching is complete, the entire clock switching circuit is turned off until another clock switching occurs.

Parallel analog sampling circuit and analog-to-digital converter system incorporating clock signal generator generating sub-sampling clock signals with fast and precisely-timed edges

Abstract: The analog sampling circuit samples an analog input signal at intervals of time precisely defined by a master clock signal. The analog sampling circuit comprises N track-and-hold circuits and a clock signal generator. Each of the track-and-hold circuits includes a clock signal input. The clock signal generator includes a clock window signal generator and N gate circuits. The clock window signal generator comprises an input connected to receive the master clock signal, and N outputs, derives clock window signals from the master clock signal and feeds one of the clock window signals to each of the outputs. The clock window signals have imprecisely-timed edges. Each of the N gate circuits generates a sub-sampling clock signal with logic states defined by one of the clock window signals and with edge timings defined by the master clock signal independently of the imprecisely-timed edges of the clock window signal, and comprises a first input, a second input and an output. The first input is connected to one of the outputs of the clock window signal generator, the second input is connected to receive the master clock signal and the output is connected to the clock signal input of one of the track-and-hold circuits. The N-channel analog-to-digital conversion system includes the analog sampling circuit just described and an analog-to-digital converter connected to the analog output of the each of the N track-and-hold circuits.

Low-jitter on-chip clock for RSFQ circuit applications

Abstract: The ultra-narrow linewidth of a long Josephson junction (LJJ) oscillator offers low timing jitter as a clock source. In this paper, we will discuss the improvement of an LJJ clock by using an annular geometry. We demonstrate the integration of an annular LJJ with a clock decimator which consists of a serial chain of toggle-flip-flops (TFFs). Each TFF divides its input frequency by a factor of 2. We have also developed a clock frequency selector. The clock selector circuit can choose either the master clock fm or one of its sub-harmonics (fm/2m, m = 1 to n), based on the select inputs. The generation of a set of clocks will enable us to integrate the on-chip LJJ clock with a flash analogue-to-digital converter.

Methods and systems for column line selection in a memory device

Abstract: An integrated circuit device is provided having a column selection circuit which activates the column selection line output responsive to a column latch signal rather than a data command signal. The leading edge of the column latch signal is used to generate a master clock signal and to latch the selected address. The master clock signal is delayed and a column decoder circuit decodes the latched selected address to activate the appropriate column selection line output responsive to the delayed clock. As activation of the column selection line output initiates placement of the desired sense amplified bit line signal on the local input and output lines, the voltage differential on the local input and output lines can begin to develop earlier than with the prior art approaches. Therefore, the voltage levels on the local input and output lines may reach the desired levels before or shortly after the data command signal is activated thereby allowing the input and output sense amplifier to be enabled and output the read data shortly after the data command signal is activated. Write operations may be similarly supported. Methods are also provided.

Clock synchronization in telecommunications network using system frame number

Abstract: A telecommunications system (18) capitalizes employment of a system frame number (SFN) for synchronizing plural real time clocks (206) provided at one or more nodes of the network. System frame signals (e.g., pulses) are distributed from a source (210, 310) to processors (202) having slave clocks (206S) that need to be synchronized with a master clock. A master processor (202M, 302T) sends a clock set message (500) to the processors, the clock set message including a reference master clock time (506) and a reference system frame number (504). The recipient processors which receive the clock set message resynchronize their respective slave clocks using the reference master clock time and the reference system frame number. In one mode, the clock set message directs the recipient processors to set their respective slave clocks to the reference master clock time upon the recipient processors obtaining the reference system frame number. In another mode, the clock set message advises the recipient processors of an actual master clock time at the reference system frame number, thereby enabling the recipient processor to calculate an adjusted slave clock time.