Showing papers on "Memory controller published in 1996"

Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed

Abstract: A memory controller for a microprocessor including apparatus to both detect a failure of speculation on the nature of the memory being addressed, and apparatus to recover from such failures.

Non-volatile memory with embedded programmable controller

Abstract: Computer systems may be provided with additional performance for demanding applications while adding little additional hardware. For example, a slave device for a host computer system combines an embedded programmable controller with non-volatile memory, local RAM, and interface logic. The host computer system treats the slave device as if it would be a hierarchical memory system such as a conventional disk drive on which it may store and retrieve files. Additionally, the host computer system may program the controller to perform operations on stored information, including image processing and/or data compression. The non-volatile memory may include a disk drive, writable CD-ROM, optical drive, or non-volatile solid state memory.

Single chip multiprocessor architecture with internal task switching synchronization bus

Abstract: A plurality of processors which can be the same or different are formed on a single integrated circuit chip together with a memory controller and an I/O controller, and are interconnected by a data transfer bus. The processors can have larger word lengths and operate at higher speeds than comparable single chip processors due to reduced latency and signal path lengths. The processors are further interconnected by a processor synchronization bus which enables one processor to cause another processor to perform a task by generating an interrupt and passing the required parameters. The parameters can be passed via shared memory, or via a bidirectional data section of the processor synchronization bus. A processor running a large scale CAD or similar application can cause a smaller processor to perform I/O tasks in native code. A multiprocessor system can be configured as including a Single-Chip module (SCM), a Multi-Chip Module (MCM), Board-Level Product (BPL), or as a box-level product which includes a power supply.

Multiple bank memory with auto refresh to specified bank

Abstract: A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes multiple bank memory arrays. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, an auto-refresh command controlling an auto refresh operation to a specified one of the multiple bank memory arrays.

Apparatus and method for aborting un-needed instruction fetches in a digital microprocessor device

Abstract: The present invention minimizes unneeded memory accesses by providing a digital processor having control circuit for terminating on-going memory accesses, and by a data transfer circuit that allow jump instructions to be detected sooner in the decode unit. The digital processor includes a decode unit, fetch unit and a memory controller. When the decode unit of the present invention processor determines that a discontinuity must occur in the instruction fetch sequence, it asserts a "jump taken" signal to the fetch unit to indicate that any pre-fetched instruction codes are to be discarded and that fetching is to resume at a new fetch program counter (FPC) value. If the fetch unit is currently stalled because of an outstanding request to the memory controller unit, then the fetch unit asserts an "abort" signal to the memory controller. The memory controller unit interprets the abort signal to mean that the current memory access activity is to be terminated as soon as possible, such that aborting the current operation does not corrupt the stored content of the memory element. In addition to the abort signal, the memory controller unit may assert A "partial-done" signal that informs the fetch unit that some fraction of the current request has been completed. The size of the fractional data made available to the fetch unit will correspond to some size or alignment criteria such that the fetch unit may then be able to forward one instruction code to the decode unit. If the forwarded instruction is a "taken" jump, then the decode unit will be able to abort the current fetch request sooner than if it had to wait for the full request to be satisfied.

Secure memory management unit for microprocessor

Abstract: A secure embedded memory management unit for a microprocessor is used for encrypted instruction and data transfer from an external memory. Physical security is obtained by embedding the direct memory access controller on the same chip with a microprocessor core, an internal memory, and an encryption/decryption logic. Data transfer to and from an external memory takes place between the external memory and the memory controller of the memory management unit. All firmware to and from the external memory is handled on a page-by-page basis. Since all of the processing takes place on buses internal to the chip, detection of clear unencrypted instructions and data is prevented.

Standardized flash controller

Abstract: A flash memory controller operates a flash memory array comprising a plurality of different types of flash memory chips. The CPU interacts with the array by issuing generic commands through a single Memory Technology Driver (MTD), while the controller translates the generic commands into commands specific to the chip comprising the portion of the array being addressed. The controller operates each of the flash chips which comprises the flash memory array, and presents to the CPU a memory system comprised of a single addressable entity. According to a further feature of the invention, the controller is embedded into each of the flash chips in an array in order to further reduce overhead costs.

Quick recovery of write cache in a fault tolerant I/O system

Abstract: A method for recovering data from a cache memory of a second storage controller by access to a cache memory of a first storage controller is presented. The storage controllers are coupled by a private common data path. The method includes copying metadata corresponding to the data stored in the cache memory of the second storage controller to the cache memory of the first storage controller through the private common data path. The metadata may include pointers to and the size of the data. After copying the metadata pointers, the data in the cache memory of the second storage controller is established in the cache memory of the first storage controller. As a result, the entire set of data does not need to be totally recovered to the hard disk before resuming host communications in a recovery operation, which may take a relatively long time. Instead, if a controller fails, only a portion of the data in the cache of the failed controller, the data describing the recovery information, needs to be incorporated into the "dirty" cache of the remaining controller before communications with the host are resumed.

Memory controller with low skew control signal

Abstract: An apparatus and a method are provided for delaying or skewing a control signal provided to an electronic device such as a memory device with an alignment delay, such that the overall delay associated with the alignment delay and the propagation delay associated with outputting the control signal to the electronic device substantially equals one or more integral cycles of a clock signal. As a result, the control signal received at the electronic device is substantially aligned with the clock signal. This results in synchronizing or realigning the asynchronously-generated control signal back into a synchronous environment. The apparatus and method have unique applicability when used in memory controllers and the like for handling memory accesses with one or more memory devices, in particular with memory devices having enhanced memory transfer modes or higher transfer speeds, where even a small amount of skew between a control signal and a clock signal may significantly degrade performance. A propagation delay, or delay factor, associated with outputting the control signal to the electronic device is computed based upon the process factor for the apparatus, as well as any temperature and/or voltage variations. In addition, the delay factor may be modified dynamically to account for real-time voltage and/or temperature variations.

Apparatus and method for multiple-level storage in non-volatile memories

Abstract: A storage control circuit determines a programmed threshold voltage VtP of a storage cell in which the transistor threshold voltages VtT of the cell may overlap while the logical threshold voltages VtL remain distinct. In one embodiment, sixteen distinctive levels are stored in a storage cell within a 2.5 V range so that a single memory cell supplies four bits of information storage per cell, quadrupling the memory capacity per cell as compared to conventional single-bit storage cells. In an embodiment, a nonvolatile memory circuit includes a nonvolatile memory array with a plurality of memory cells and a plurality of decoders connected to the nonvolatile memory array. The plurality of decoders decode addresses to the nonvolatile memory array. The nonvolatile memory circuit also includes a voltage controller connected to the nonvolatile memory array, a programming controller connected to the plurality of decoders and connected to the voltage controller, a plurality of sense amplifier and reference cells connected to the plurality of decoders for sensing a memory cell at a selected memory cell address of the plurality of memory cells in the nonvolatile memory array and connected to the programming controller for receiving the sensing mode signal, and a level conversion circuit having input terminals connected to the plurality of sense amplifier and reference cells and having an output terminal connected to the programming controller for communicating a level feedback signal. The voltage controller controls a programming voltage amplitude applied to the nonvolatile memory array. The programming controller selects a memory cell address, a nonvolatile memory array programming voltage amplitude, and a sensing mode signal.

Internetworking device with enhanced protocol translation circuit

Abstract: A special memory overlay circuit uses a first DRAM buffer memory in combination with a second faster SRAM buffer memory to reduce the time required to translate information into different network protocols. Packet data is stored in the DRAM buffer memory and packet headers requiring manipulation are stored in the SRAM buffer memory. Because the SRAM has a faster data access time than the DRAM buffer memory, a processor can reformat the packet header into different network protocols in a shorter amount of time. Packet headers also use a relatively small amount of memory compared to remaining packet data. Since the SRAM buffer memory is only used for storing packet headers, relatively little additional cost is required to utilize the faster SRAM memory while substantially increasing network performance.

Flexible processor-driven SCSI controller with buffer memory and local processor memory coupled via separate buses

Abstract: The invented controller is the combination of: an intelligent interface to a SCSI bus, a multi-port buffer memory manager, a formatter, and a local processor port. With the addition of a few components for the device-level interface, the invented controller along with a buffer RAM, a local processor system, and an optional data separator completes a high performance disk, or other mass storage, controller subsystem. The invention is particularly directed to (1) the dual use of a buffer memory as data buffer storage and for storage of instructions to be executed by a SCSI-protocol processor, (2) the architecture of the interface to the SCSI bus, and (3) the instruction set of the SCSI-protocol processor.

DMA controller for memory scrubbing

Abstract: A fault tolerant computer system is described in which a direct memory access controller examines the check bit data on every data element that is accessed by the system. The address of any data element that is found to have an error in the check bit data is stored by the direct memory access controller, the check bit data is used by the direct memroy access controller to correct the error, and the corrected data element is rewritten to the original storage address. By the use of this arrangement, the central processing unit or units of the computer system are free to perform other tasks, thus improving system throughput, and preventing the accumulation of data element errors in the memory.

Prepaging during PCI master initiated wait cycles

Abstract: A system is disclosed for optimizing data transfer times between an external Master device and main memory. The system includes an integrated processor with a PCI bridge for orchestrating data transfers with the PCI Master over the PCI bus, and a memory controller for controlling access to the main memory. During burst cycles of the PCI Master, the PCI bridge expedites data transfers by providing the memory address to the memory controller early during periods when the PCI Master is slow in transmitting or receiving data. When the PCI Master is unable to respond in a timely fashion, and while the PCI bridge is in control of the local bus, the PCI bridge asserts a MEMWAIT signal to the memory controller to indicate the need to throttle down a data transfer. At substantially the same time, the PCI bridge supplies the memory controller with the next memory address to enable the memory controller to open the appropriate page (and/or precharge the last page) in the memory to expedite subsequent data transfers by asserting (and/or deactivating) the proper row address strobe (RAS) lines. When MEMWAIT is deasserted by the PCI bridge, the memory controller immediately responds by asserting the column address strobe to drive in or drive out the data. As a result of opening the page in memory early, the system potentially saves the RAS access time (t RAC ) and the RAS precharge time (t RP ) in the data transfer.

Device for controlling memory data path in parallel processing computer system

Abstract: A memory data path controller for a large-scale parallel processing computer system in which, when a network interface and bus interface request access to a single-port memory, a dual path controller dividedly stores memory access requests in network queue and bus queue. This allows a single-port DRAM to be used as a dual-port memory device. Further, the network queue and bus queue are multi-staged to store sequential memory requests and transmit reading/writing data of the network queue or bus queue to the DRAM memory.

Data processing system having memory controller for supplying current request and next request for access to the shared memory pipeline

Abstract: A router includes synchronous dynamic random access memory (SDRAM) based shared memory, with a controller configured to control the order in which the SDRAM access is granted to a plurality of interfaced components. In one embodiment, the controller's configuration minimizes the amount of time data from a particular source must wait to be read to and written from the SDRAM, and thus minimizes latency. In a different embodiment, the controller's configuration maximizes the amount of data read to and written from said SDRAM in a given amount of time and thus maximizes bandwidth. In yet another embodiment, characteristics of the latency minimization embodiment and the bandwidth maximization embodiment are combined to create a hybrid configuration.

Video/audio data supplying device

Abstract: When the input output controller 22 receives request data through the modem 42, the input output controller 22 controls the memory controller 25 to retrieve an AV stream and a BGV stream from the memories and to transfer the streams to the multiplexer 30. The memory controller 25 retrieves a BGV stream from the BGV memories 26a, 26b, and 26c and an AV stream from the AV memories 27a, 27b, and 27c. When receiving the BGV stream and the AV stream, the multiplexer 30 divides the AV stream into a lyric stream and a music stream. The multiplexer 30 composes the lyric stream and the BGV stream into a video stream. The multiplexer 30 time-divisionally multiplexes the video stream and the music stream and outputs the multiplexed stream as a video/music stream.

Data merging method and apparatus for shared memory multiprocessing computer systems

Abstract: In a shared memory multiprocessing computer system, multiple processors can cache copies of a shared data block in their local cache memories and independently modify their cached copies. The cached copies are later merged in a global memory with the shared data block. With each cached copy, a bitmask consisting of a plurality of flags associated with elements of the cached copy also is stored in the local memories. A local memory controller tracks which elements of the cached copies are modified by setting the bitmask flags associated with such elements. When merging, only modified elements of the cached copies are stored in the originating data block as indicated by the bitmask flags.

MPEG decoder system and method having a unified memory for transport decode and system controller functions

Abstract: An MPEG decoder system and method for performing video decoding or decompression which includes a unified memory for multiple functions according to the present invention. The video decoding system includes transport logic, a system controller, and MPEG decoder logic. The video decoding system of the present invention includes a single unified memory which stores code and data for the transport, system controller and MPEG decoder functions. The single unified memory is preferably a 16 Mbit memory. The MPEG decoder logic includes a memory controller which couples to the single unified memory, and each of the transport logic, system controller and MPEG decoder logic access the single unified memory through the memory controller. The video decoding system implements various frame memory saving schemes, such as compression or dynamic allocation, to more efficiently use the memory. In one embodiment, the memory is not required to store reconstructed frame data during B-frame reconstruction, thus considerably reducing the required amount of memory for this function. Alternatively, the memory is only required to store a portion of the reconstructed frame data. In addition, these savings in memory allow portions of the memory to also be used for transport and system controller functions. The present invention thus provides a video decoding system with reduced memory requirements.

HDLC integrated circuit using internal arbitration to prioritize access to a shared internal bus amongst a plurality of devices

Abstract: This invention relates to an integrated HDLC circuit of the type including at least one HDLC controller and one DMA controller, and means for organizing the access to a first external bus for connection to an external memory, via an internal bus to which are connected different entities, which require to have access to the external memory, the internal bus being connected to the first external bus via a memory controller integrated in the HDLC circuit.

Memory controller and method of memory access sequence recordering that eliminates page miss and row miss penalties

Abstract: An improved memory controller is disclosed for accessing a computer memory, which consists of a plurality of banks of page mode memory cells and is connected to a CPU via a split transaction bus with out-of-order completion capability. The improved memory controller comprises: (a) a unified command queue for receiving a memory access command; (b) a plurality of command queues equalling in number to the number of the memory banks; (c) a dispatch logic for dispatching the memory access command into one of the command queues in accordance with which memory bank the access command is to access; (d) a selection logic for selecting one of the command queues as an active command queue to execute a command, wherein all the non-selected command queues are placed on a standby status as standby command queues; and (e) switching logic provided in the selection logic for switching the command execution from the active command queue to a standby command queue, which is made active according to a predetermined criterion, when a page miss is detected or when the active command queue is empty. The switching logic also causes one of the standby command queues to perform a row address selection when the active command queue is accessing said computer memory. With the improved memory controller, penalties associated with row miss and/or page miss are eliminated. As a result, the average memory access latency is minimized and overall memory utilization efficiency is enhanced.

Apparatus and method for dynamic memory refresh

Abstract: A dynamic memory refresh apparatus includes a programmable refresh interval generator that generates an interval for generating a refresh request signal. The refresh interval time is based on the manufacturer specified DRAM cycle time, the system clock period, and the number of memory segments on the memory board that are supported by the computer system. The refresh interval time substantially maximizes the time between refreshes of a particular DRAM module. The dynamic refresh apparatus also includes a memory segment pointer generator that generates a memory segment pointer. The memory segment pointer points to the next memory segment to be refreshed. The memory segment pointer is generated such that the memory segments are selected in a staggered manner. In addition, the dynamic memory refresh apparatus includes a refresh request generator that generates a refresh request signal for the memory segment pointed to by the memory segment pointer. The refresh request generator generates the refresh request only for segments for which data is present.

Memory system and method for selecting a different number of data channels depending on bus size

Abstract: A memory system includes a main memory and a memory controller, the main memory including at least one block which has a plurality of banks. The memory controller includes a plurality of data channels each of which can access at least one bank in the main memory. Each data channel comprises a write first-in-first-out (FIFO) buffer for efficiently supporting cache purge operations and normal write operations, and a reflective write FIFO buffer for efficiently supporting coherent read with simultaneous cache copyback operations. The memory controller selects the proper FIFO or FIFOs depending on the type of data transaction, and selects the proper channel or channels depending on the system bus size, the data transaction size, and the status of cache FIFO(s). The memory system can efficiently support data transactions having different data lengths or sizes from a byte to a long burst. The memory system can support different bus and processor systems and different data transactions in a highly efficient manner.

CPU, memory controller, bus bridge integrated circuits, layout structures, system and methods

Abstract: An integrated circuit includes a single chip (102) that has a microprocessor (702), a memory controller unit (718), an internal bus (714) connecting the microprocessor (702) and the memory controller unit (718), and an external bus to internal bus interface circuit (716). The microprocessor (102) occupies a substantially rectangular region on a substrate (802). The memory controller unit (718) occupies a first strip along one side of the microprocessor unit (702) accessible via the bond pads broadside to the first strip. Other circuits, systems, and methods are disclosed.

Method of rewriting data in a microprocessor additionally provided with a flash memory

Abstract: The present invention relates to a method of rewriting data in a microcomputer additionally provided with a flash memory having a refresh mode, in which the data retained in an area arbitrarily specified in the flash memory is transferred to a RAM for temporary evacuation and after the data in the area has been erased, the data evacuated to the flash memory is written into the area again.

Computer system having distributed compression and decompression logic for compressed data movement

Abstract: A computer system having distributed compression and decompression logic for compressed data movement within the computer system. This provides increased efficiency and reduced bus bandwidth requirements. The computer system includes various standard components, including a CPU, chip set logic, main memory, one or more expansion buses, and various peripheral devices coupled to the expansion buses. Various devices may be connected to the PCI bus, including graphics accelerator hardware, audio logic, a hard drive, and a network interface card, and other multimedia devices, as desired. In the preferred embodiment, the bridge logic and/or memory controller, one or more of the multimedia devices, the hard drive, and the network interface controller each includes compression/decompression (codec) logic which performs compression and decompression operations. Thus, when a device desires to perform a transfer on the bus, the codec in the device preferably compresses the data before transferring the data onto the bus. The receiving or destination device includes codec logic which receives the compressed data and decompresses the data, and the decompressed data is then used or stored by the device. Thus, the majority of data transfers on the bus are compressed data transfers, i.e., comprise transfers of compressed data. This optimizes or reduces the required bus transfer bandwidth.

Dynamic spare column replacement memory system

Abstract: An MxN dynamic spare column replacement memory system for storing M N-bit data words includes a random access memory (RAM) formed by a rectangular array of M rows and N+S columns of single-bit memory cells. Each row has a unique address and stores an N-bit word using a selected set of N of its N+S cells. An N-line parallel data bus provides data access to the DRAM. Responding to a switching instruction from a switch controller at the start of each memory access cycle, a crossbar switch selectively connects each of the N lines of the data bus to a separate one of the N+S columns. Thus during a memory read or write access cycle the N data lines access N cells of an addressed row columns. The remaining S cells of the row are unused. A host computer occasionally checks the DRAM for defective memory cells, and upon finding a defective cell or cells in any row, the host stores the row address and a switching instruction in the switch controller. At the beginning of each memory access cycle, the switch controller compares the DRAM address to its stored list of addresses of rows having a defective cell. If the current DRAM address matches a stored address, the switch controller switches data bus lines from columns containing the defective cell to spare columns in accordance with a switching instruction stored with the address. Thus spare cells are assigned for replacement of defective cells on an address-by-address basis.

Memory access system with overwrite prevention for overlapping write operations

Abstract: The present invention operates within a data processing system including a processor coupled to a memory controller unit which is coupled to memory used for storing and retrieving data. The memory controller unit provides separate read and write data pipelines, allowing write operations to overlap preceding read operations. The present invention selectively delays a certain limited number of write operations, delaying a write operation only if it is directed to the same memory address as that of a preceding read operation. By delaying this limited number of write operations, the present invention substantially preserves the advantages of write overlap while preventing the problem of overwrite. An alternative embodiment of the present invention selectively suppresses error writeback operations associated with a read operation if the read operation is followed by a write operation to the same address.

Computer system with system ROM including serial-access PROM coupled to an auto-configuring memory controller and method of shadowing BIOS code from PROM

Abstract: A computer system having a processor is provided with a memory controller serially coupled to a serial-access programmable read-only-memory ROM (PROM) through a serial PROM interface of the controller. A random-access memory controller randomly accesses the BIOS code in the serial PROM during power-up of the computer system in response to read requests from the CPU. If the memory controller cannot immediately process the read requests from the CPU, the controller creates wait states for the CPU. An auto-configuring memory controller sequentially accesses the entire BIOS code in the serial PROM during power-up and prior to the running of the CPU and copies it to a portion of base memory, eliminating random accesses to the PROM.

Modular high-capacity solid-state mass data storage device for video servers including a switch for simultaneous multi-viewer access

Abstract: A modular solid-state mass data storage device providing high-density, high capacity storage of numerous full-length movies for video server applications. The mass data storage device employs a modular pipeline architecture in which a distributed array of controller/memory modules is arranged in parallel controller/memory channels on one or more controller/memory cards. The modular pipeline architecture, in which each controller/memory channel has multiple controller/memory modules connected in a serial chain by address, data and control buses, allows the number of controller/memory modules in each channel and the number of controller/memory channels to be selected to accommodate a desired storage size and transfer rate, without an undesirably high latency time. An asynchronous transfer mode (ATM) switch allows multiple viewers to access the movies stored in the mass data storage device with independent video cassette recorder (VCR)-like control of the movie being watched. In a disclosed embodiment, the controller/memory modules in each channel are connected to first and second buses which extend from a data format module, the first bus also extending from the last controller/memory modules in each channel back to the data format module. The data format module provides data formatting, synchronization and error correction for the stored movies. In the disclosed embodiment, each controller/memory module includes an array of dynamic random access memory (DRAM) chips, and multiple controller/memory modules are packaged in standard memory module packages, such as single in-line memory module (SIMM) packages.