Showing papers on "Moore's law published in 2006"

Establishing Moore's Law

Abstract: The seemingly unshakeable accuracy of Moore's law - which states that the speed of computers; as measured by the number of transistors that can be placed on a single chip, will double every year or two - has been credited with being the engine of the electronics revolution, and is regarded as the premier example of a self-fulfilling prophecy and technological trajectory in both the academic and popular press. Although many factors have kept Moore's law as an industry benchmark, it is the entry of foreign competition that seems to have played a critical role in maintaining the pace of Moore's law in the early VLSI transition. Many different kinds of chips used many competing logic families. DRAMs and microprocessors became critical to the semiconductor industry, yet were unknown during the original formulation of Moore's law

Moore's law meets its match (system-on-package)

Abstract: This paper describes the system-on-package (SOP) approach to miniaturization developed at the Microsystems Packaging Research Center at the Georgia Institute of Technology. Representing a radically different approach to systems, SOP combines IC with micrometer-scale thin film versions of discrete components, and it embeds everything in a new type of package so small that eventually handhelds will become anything from multi- to megafunction devices. It shrinks bulky circuit boards with their many components and makes them nearly disappear. Thus, SOP technology yields far more in system miniaturization than can be expected from Moore's law, which deals only with transistors in ICs

Marching to the beat of Moore's Law

Abstract: Area density scaling in integrated circuits, defined as transistor count per unit area, has followed the famous observation-cum-prediction by Gordon Moore for many generations. Known as "Moore's Law" which predicts density doubling every 18-24 month, it has provided all important synchronizing guidance and reference for tools and materials suppliers, IC manufacturers and their customers as to what minimal requirements their products and services need to meet to satisfy technical and financial expectations in support of the infrastructure required for the development and manufacturing of corresponding technology generation nodes. Multiple lithography solutions are usually under considerations for any given node. In general, three broad classes of solutions are considered: evolutionary - technology that is extension of existing technology infrastructure at similar or slightly higher cost and risk to schedule; revolutionary - technology that discards significant parts of the existing infrastructure at similar cost, higher risk to schedule but promises higher capability as compared to the evolutionary approach; and last but not least, disruptive - approach that as a rule promises similar or better capabilities, much lower cost and wholly unpredictable risk to schedule and products yields. This paper examines various lithography approaches, their respective merits against criteria of respective infrastructure availability, affordability and risk to IC manufacturer's schedules and strategy involved in developing and selecting best solution in an attempt to sort out key factors that will impact the decision on the lithography choice for large-scale manufacturing for the future technology nodes.

Overcoming research challenges for CMOS scaling: industry directions

Abstract: The development of silicon technology has been, and will continue to be, driven by system needs. The continuous and systematic increase in transistor density and performance, guided by CMOS scaling theory (Dennard et al., 1974) and described in "Moore's Law" (Moore, 1975), has been a highly successful process for the development of silicon technology for the past 40 years. As the silicon industry moves into the 45 nm node and beyond, significant technology challenges are imposed by silicon CMOS device scaling. Two of the most important challenges are the growing standby power dissipation and the increasing variability in device characteristics. These complaints are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. They are frequently cited as the reason Moore's Law is "broken", or why CMOS scaling is coming to an end. Industry directions for addressing these challenges are developing along three primary extending silicon scaling through innovations in materials and device structure; expanding the level of integration through three-dimensional structures comprised of silicon through-via holes and chip stacking in order to enhance functionality and parallelism; and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials, and new processes, such as spintronics, carbon nanotubes, nanowires, or molecular systems

An Industry Perspective on Current and Future State of the Art in System-on-Chip (SoC) Technology

Abstract: In fast-moving consumer electronics markets where product lifetimes may be measured in months rather than years, fast time-to-market development of the system-on-chip solutions that lie at the heart of these products has become critical to commercial success New semiconductor process technologies have the potential to integrate ever greater functional complexity onto realistically priced silicon chips Yet there still remains a significant design gap between what can theoretically be integrated onto silicon and what can be efficiently designed onto it In addition, the advent of sub-100-nm process technologies has seen an end to the speed and power consumption scaling that the industry has been used to This paper examines the current state of the art in SoC technology and identifies some of the challenges that lie ahead if the relentless progress of Moore's Law is to continue fuelling ever more advanced and affordable consumer electronics products It also looks at the system-in-package solutions that are increasingly being used to achieve levels of functional integration that Moore's Law on its own cannot provide

The Impact of Moore's Law

Abstract: The ever-increasing number of integrated transistors on silicon chips has earned fame as "Moore's Law," according to which miniaturization and "cleverness" (more compact device designs) reduce cost-per-element, increase storage capacity, and promote reliability. Low-cost integrated electronics have revolutionized everyday life and expanded the role of computation in science and engineering.

RAMP: research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform

Abstract: Summary form only given. The vast majority of computer architects believe the future of the microprocessor is hundreds to thousands of processors ("cores") on a chip. Given such widespread agreement, it's surprising how much research remains to be done in algorithms, computer architecture, networks, operating systems, file systems, compilers, programming languages, applications, and so on to realize this vision. Fortunately, Moore's law has not only enabled dense multi-core chips, it has also enabled extremely dense FPGAs. Today, one to two dozen soft cores can be programmed into a single FPGA. With multiple FPGAs on a board and multiple boards in a system, 1000-processor designs can be economically and rapidly explored. To make this happen, however, requires a significant amount of infrastructure in hardware, software, and what we call "gateware", the register-transfer level models that fill the FGPAs. By using the Berkeley Emulation Engine boards that were created for other purposes, the hardware is already done. A group of architects plan to design the gateware, create this infrastructure, and share the results in an open-source fashion so that every institution could have their own. Such a system would not just invigorate multiprocessors research in the architecture community. Since processors cores can run at 100 to 200 MHz, a large scale multiprocessor would be fast enough to run operating systems and large programs at speeds sufficient to support software research. Moreover, there is a new generation of FPGAs every 18 months with capacity for twice as many cores and run them faster, so future multiboard FPGA systems are even more attractive. Hence, we believe such a system would accelerate research across all the fields that touch multiple processors. Thus the acronynm RAMP, for Research Accelerator for Multiple Processors. RAMP has the potential to transform the parallel computing community in computer science from a simulation-driven to a prototype-driven discipline, leading to rapid iteration across interfaces of the many fields of multiple processors, and thereby moving much more quickly to a parallel foundation for large-scale computer systems research in the 21st century.

Where CMOS is going: trendy hype vs. real technology

Abstract: The development of silicon technology has been, and will continue to be, driven by system needs. Traditionally, these needs have been satisfied by the increase in transistor density and performance, as suggested by 'Moore's Law" and guided by CMOS scaling theory. As the silicon industry moves towards the 45nm node and beyond, the two most important challenges cited are the growing standby power dissipation and the increasing variability in device characteristics. These complaints are cited as the reason Moore's Law is "broken", or why CMOS scaling is coming to an end. Actually, these effects are the embodiments of CMOS technology's approach to atomistic and quantum-mechanical physics boundaries. However, the infusion of new materials and device structures will extend the development lifetime of silicon CMOS by at least ten years. Cooperative circuit/technology co-design, and architectures developed concurrently with these new device innovations will provide a comprehensive solution to the challenges of deep submicron CMOS

The Moore’s Law for photonic integrated circuits

Abstract: We formulate a “Moore’s law” for photonic integrated circuits (PICs) and their spatial integration density using two methods. One is decomposing the integrated photonics devices of diverse types into equivalent basic elements, which makes a comparison with the generic elements of electronic integrated circuits more meaningful. The other is making a complex component equivalent to a series of basic elements of the same functionality, which is used to calculate the integration density for functional components realized with different structures. The results serve as a benchmark of the evolution of PICs and we can conclude that the density of integration measured in this way roughly increases by a factor of 2 per year. The prospects for a continued increase of spatial integration density are discussed.

The rationale and paradigm of "more than Moore"

Abstract: For several decades, microelectronic industries and relevant academic communities have been spending tremendous effort in developing and commercializing the Moore's law, leading to not only many breakthroughs and revolution in ICT, but also noticeable changes in the way of living of human being. While this trend is still be valid, pushing microelectronics to the nanoelectronic era, in recent years, there are ever-increasing awareness, R&D effort and business drivers to speed up the development and application of "more than Moore" that are based upon or derived from silicon technologies but do not scale with Moore's law (with typical examples as RF, power/HV, sensor/actuator/MEMS, SiP, SSL, etc.). The future business opportunities and technology challenges are the innovations and effective integration of Moore's law focusing mainly on digital function with MtM focusing mainly on non-digital function and heterogeneous integration. Starting from the rationale of MtM, this paper highlights some strategic research issues of sensors and actuators within the technology domain MtM. Some issues related to the paradigm of MtM, covering industrial vision, strategy and business models, is also discussed.

Living with Failure: Lessons from Nature?

Abstract: The resources available on a chip continue to grow, following Moore's Law. However, the major process by which the benefits of Moore's Law accrue, which is the continuing reduction in feature size, is predicted to bring with it disadvantages in terms of device reliability and parameter variability. The problems that this will bring are underlined by the predictions from an Intel commentator: within a decade we will see 100 billion transistor chips. That is the good news. The bad news is that 20 billion of those transistors will fail in manufacture and a further 10 billion will fail in the first year of operation.

The Wider Impact of Moore's Law

Abstract: Three very large, independent phenomena, i.e. the enormous growth of the semiconductor industry, the commoditization of the computer industry and the emergence of a huge software industry have created the economic framework that has held Moore's Law in place for so long. Moore's Law has become an economic law expressing the rate at which each product generation lasts long enough to be (marginally) profitable for the systems vendors, and yet provides new product introductions to customers at a pace at which they will consider them seriously.

Lithography and the Future of Moore's Law, Copyright 1995 IEEE. Reprinted with permission. Proc. SPIE Vol. 2437, pp. 2–17

Abstract: Semiconductor technology has made its great strides as a result of ever increasing complexity of the products produced exploiting higher and higher density to a considerable extent the result of progress in lithography. This article reviews the history and past performance of Moore's Law relative to predictions and shows where the advances have come from.

The 3rd dimension-More Life for Moore's Law

Abstract: In accordance with continuing push for smaller and faster electronics, there is strong demand for further miniaturization and higher performance of mobile and other digital devices Three-dimensional interconnect with through silicon via is one of the solution with best potential to extend Moore's Law 3D interconnect had the benefits of lower cost, higher performance, smaller form factor and heterogeneous integration for chips manufacturing Thermal dissipation, process technology and circuit design are the top three issues for 3D IC success For Si processing, the major challenges are the patterning and the fill of the through wafer via, wafer thinning, die/wafer bonding and its alignment We need to carefully address those issues before we can proceed to mass production

Strategic Research Agenda of "More than Moore"

Abstract: In the past decades, the main stream of microelectronics progresses is mainly powered by Moore's law, with two focused development arenas, namely, IC miniaturization down to nano dimension, and SoC based system integration. While microelectronics community continues to invent new solutions around the world to keep Moore's law alive, there are ever-increasing awareness, R&D effort and business drivers to push the development and application of `More than Moore" (MtM) that are based upon or derived from silicon technologies but do not scale with Moore's law (with typical examples as RF, Power/HV, Sensor/Actuator/MEMS, SiP, SSL, etc.). Starting from a short overview about the motivation and activities of Eniac (European Nanoelectronics Initiative Advisory Council), this paper will highlight part of the strategic research subjects for the technology domain of "More than Moore".

Moore's Law – The Genius Lives On

Abstract: Walking through the four decades since Gordon Moore made his wonderful prediction: The 1970's was the era of invention; the 1980's, the era of scaling and manufacturing science, making Moore's Law viable and affordable. The 1990's was an era of manufacturing and speed. As we enter the 21st century, the challenge is to exploit the transistor integration capacity provided by Moore's Law, deliver increasingly higher performance, and yet stay within the power limits imposed in each platform segment.

The innovation curve [Moore's law in semiconductor industry]

Abstract: The world of the computer has been marked by rapid change since its very inception. In the hardware domain, we think of change as being driven by Moore's law, the observation of Gordon Moore concerning the improvements in integrated circuits. Viewed from a distance, Moore's law has seemed to be a natural phenomenon, something akin to gravity. Every 18 months, processors are faster, memories are larger, and prices are lower. However, as we probe the operation of the semiconductor industry, we quickly find that there is little natural about Moore's law. The industry has been able to achieve the targets of this law only through careful, dedicated planning. Over the past few years, these plans have taken the form of a large, collaborative document known as a "roadmap". The roadmap has been revised every three to four years with interim reports appearing between the major revisions.

Heat, speed and error limits of moore's law at the nano scales

Abstract: The evolution of microprocessor miniaturization and performance, often described by Moore's law [1, 2], is close to the saturation limit. This paper discusses the limitation of the evolution of performance and minimization process for high performance microprocessors related to noise and power dissipation. In particular, the predictions provided in a previous paper [3] are refined in order to take into account the increasing effect of leakage currents on power dissipation.

Laying down the law

Abstract: Almost all engineers are aware of Moore's law'. The phenomenon it describes has had an amazing impact on electronics over the last few decades, continually making devices cheaper, faster and smaller. Moore's law is an example of prediction about technological growth - it is not founded in laws of nature, like Ohm's Law, for example, but is essentially an economic prediction based on observations of previous trends in scientific research and industry. In this article, we take a look at a range of such laws or predictions, in particular those with relevance to communications technology understanding where they have come from and what their impact might be in the future.

Can 3-D Devices Extend Moore's Law Beyond the 32 nm Technology Node?

Abstract: Beyond 2007, when the channel length is projected to be 25 nm, effective scaling of classical planar bulk MOSFETs is expected to come to an end. Below 25 nm channel length, achieving adequate electrostatic control of short channel effects poses the most serious challenge. Non-classical double-gate, ultrathin-body transistors offer to minimize short-channel effects and allow for more aggressive scaling. Several three-dimensional (3-D) multigate structures such as FinFET, Trigate, MIGFET, ITFET have been demonstrated with good electrical characteristics down to gate lengths of 10 nm. The manufacturing of 3D devices is entirely compatible with the integration processes employed for planar CMOS MOSFETs. Provided that fabrication, yield, design, and cost issues can be rendered tractable, 3D devices are poised to breathe new life into Moore’s Law and close the gap between traditional CMOS planar MOSFETs and post-CMOS-era starting at gate lengths of 6 nm. Introduction: The Driving Forces for Transistor Scaling The 2005 revision of the International Technology Roadmap for Semiconductor Industry [1] is showing a change in technology node introduction from a two-year to a three-year cycle. A stable rate of about 30% of transistor scaling every two years, observed over the last four decades, is about to slow down to about 30% decrease of transistor size every three years. (The technology nodes are, most commonly, specified by the minimum half-pitch of first metal interconnect.) This is not the first time that the technology roadmap predicts a slow down in transistor scaling: the very first edition of ITRS (TRS in 1994) prognosticated that the technology nodes beyond half-micron, i.e. starting with 0.35μm, will require three years to be developed and deployed. The past decade appears to teach that such forecasts have been received by the industry as targets to be exceeded. The 90 nm node went into production in 2003, 65 nm node is being currently introduced into production, and 45 nm technology is expected – as per ITRS roadmap to be in production sometime during 2009-2010. However, many IDMs are striving to achieve this milestone a year or more earlier than forecasted by ITRS. Many of the front-end and back-end process challenges relate to the realization that continued CMOS scaling will require the introduction of new materials, new processes, and new transistor architectures in order to perpetuate Moore’s Law [2] for the foreseeable future. Various responses to the crucial challenge of CMOS scaling seek to reconcile the conflicting requirements of reducing the transistor area, reducing the dynamic power, and reducing off-state power consumption, while increasing the circuit performance. At the present point in time, continued transistor scaling is causing currently used front-end materials to approach their fundamental physical limits. The most prominent example is the disappearing gate silicon dioxide approaching a physical thickness of two atomic layers. The limited ability of photolithography to produce small features in photoresist compounds further the scaling predicament. End of Conventional Scaling and Forces Driving the MOSFET Development When mulling possible alternatives to the planar MOSFET, it is instructive to take a closer look at the forces driving future CMOS technology development. For leading-edge logic chips, the ITRS road map updated in 2005 [1] postulates continued rapid scaling in the physical gate length and other transistor dimensions. Scaling allows to squeeze more transistors into the same space and realize new or more functionalities. Fig.1 shows the ITRS view on the historical overall trend of doubling of transistor count per microprocessor every 18-24 months heading toward 1 billion transistors in a cutting edge microprocessor in 2007. Smaller footprint of a chip results in a higher yield. With scaling it is possible to produce chips with more transistors within a given cost and power consumption window. Thus, besides performance, yield related to the smaller footprint of the circuit is, obviously, a major economic driving force in its own right, and has to be ECS Transactions, 3 (6) 3-17 (2006) 10.1149/1.2357050, copyright The Electrochemical Society

A practical algorithm for connectivity extraction for very large VLSI layouts

Abstract: Moore's law is alive and well. With designs entering the billion transistor era, there is an ever increasing demand on CAD tools to handle larger data sizes efficiently. One problem with processing large VLSI layouts is that the data to be processed is far too massive to fit into main memory. When dealing with data sets of sizes exceeding main memory, communication between the fast internal memory and the slow external memory is often the performance bottleneck and algorithms and data structures designed under the assumption of a single level of memory may not be meaningful. External memory algorithms try to optimize performance by taking into account disk accesses. One can certainly use the standard main memory algorithms for data that reside on disk but their performance is often considerably below the optimum because there is no control over how the operating system performs disk accesses. On demand thrashing can be high thus resulting in an increase in response time. Although a lot of research has been done in the recent past on efficient external-memory algorithms and data structures in general, such work in the area of VLSI computer-aided design is limited. We have designed and implemented a practical external-memory algorithm for extracting connectivity from a VLSI layout. The key to our success is two-fold. Firstly we have proposed an efficient UNION-FIND data structure which is very crucial to our algorithm.

A Moores law for photonics

Abstract: We formulate a "Moore's law" for photonic integrated circuits, based on breaking down the diverse photonics device types in photonics circuits into equivalent basic elements or functions, making a comparison with the generic elements of electronic integrated circuits more meaningful. The results serve as a benchmark of the evolution of photonic integrated circuits.

Cooling challenges and best practices for high density data and telecommunication centers

Abstract: Power and power density increase on the level of integrated circuit (IC) has been exploding following Moore's law for more than two decades (2003). Riding on the trend of IC density increase, densities on chassis enclosure as well as cabinet levels have also been increasing dramatically. A standard cabinet measuring approximately W610mm times H1880mm times D102mm that used to house only one or two computers just a decade or so ago can house more than 60 so called blade computers. Dramatic density increases inevitably lead to dramatic power consumption and heat dissipation increase. While the consequences of failure to effectively remove heat from IC devices are well understood (Iscoff, 2004), the ramifications of dramatic chassis/cabinet density and heat dissipation increases on operating environments gained recognition only recently (Mitchell, 2003). This paper includes the outlines of a book titled "Thermal Guidelines for Data Processing Environments" (2004) written by a technical committee called Mission Critical Facilities, Technology Spaces and Electronic Equipment (TC9.9) of American Society of Heating, Refrigeration, and Air-conditioning Engineers (ASHRAE). The book focuses on the convergence of data processing product specifications among major equipment vendors and outlines the data center environmental requirements that are necessary to maintain mission critical operations. The paper also describes some time tested best practices for achieving mission critical and high availability data center environments that involve high density IT equipment

Forty Years of Moore's Law: Ever Smaller Transistors and Ever Larger Wafers

Abstract: It has been forty years since Gordon Moore first posited what would one day come to be known as Moore's Law. Gordon's ideas were more than a forecast of an industry's ability to improve; they were a statement of the ability for semiconductor technology to contribute to economic growth and even the improvement of mankind in general. More importantly, Moore's Law set forth a vision of the future that harnessed the imaginations of scientists and engineers to make it all possible.

On Silicon Timing Validation of Digital Logic Gates "A Study of Two Generic Methods"

Abstract: The world of electronic industry, is working with nano-seconds domain of timings, so it's always a challenge for the electronic designers to know the exact, if not exact, then at least 99% accurate of on-silicon-delay values of their design components. By component, means, the smallest possible element for circuit designing. These components are a part of standard library, known as standard cell library. The technology trends are almost following the Moore's law and thus every year we see the technology shrinks by roughly a factor of 1.5. This trend will go on as predicted by the experts. With the increasing complexity in designs, the need for a better silicon evaluation of our building blocks is also increasing. The ASIC design flows use characterized-data for sign off, so to be aware of its accuracy is a must. As flip-flops are very important part of ASIC Design flow, the characterization of a flip flop of the ASIC library on silicon with a good accuracy is a challenge. Being a sequential element, FF's delays and power consumption are very important for ASIC designers. This study work deals with the basic understanding of these logic gates. The "two-methods" used for showing the techniques which can be readily used in the electronics industry for measuring/validating the silicon-timings for the digital gates. The methods are dummy path method and ring-oscillator method. The experimental work is performed to study the behavior of various sequential when observed under these two methods

Moore's Law and the Pace of Change

Abstract: In 1965, Gordon E. Moore, co-founder of Intel, predicted that the number of transistors in an integrated circuit would double approximately every two years. His assertion became known as Moore's Law. The nature of reference and information service has changed dramatically over the past quarter century, as has literature searching. These changes are reviewed and examined in the context of Moore's Law.