Showing papers on "Pass transistor logic published in 1971"

Mosfet logic inverter for integrated circuits

Abstract: The specification discloses a logic inverter comprised of a depletion mode MOSFET used as a resistive load between a drain supply voltage and an output and one or more enhancement mode MOSFET''s connected between output and source supply voltage. The source and gate of the depletion mode device are electrically common, and the gates of the enhancement mode devices form the logic inputs. The use of one enhancement mode device provides a simple inverter, a plurality of enhancement mode devices in parallel form a NOR gate, and a plurality of enhancement mode devices in series form a NAND gate. Combination NOR and NAND GATES may also be formed. The basic inverter circuit is also combined with a push-pull output stage to provide increased speed of operation, particularly at higher drain supply voltages. Still another embodiment utilizes an enhancement mode transistor connected between the depletion mode transistor and the output of the basic inverter stage to provide a disable function in which output drain current is switched off under all logic input conditions.

Large-scale integrated circuit testing structure

Abstract: A plurality of sequential logic circuits are connected to a shift register, both located on the same semiconductor chip. Input test data supplied at a chip input pad is routed via parallel paths interconnecting the sequential logic circuits to the shift register for performing combinatorial logic tests. The test responses are accessible to a chip output pad via the shift register. The shift register functions as virtual input/output pads so as to permit combinatorial logic testing on high density sequential logic circuits without increasing the actual input/output pad requirements of the semiconductor chip.

Power supply with temperature compensated current foldback

Abstract: A power supply with overload current foldback employs series regulating feedback circuitry for normally controlling the base potential of a series pass transistor. A current limiting transistor selectively connects the pass transistor base and power supply output terminals for reducing pass transistor drive responsive to overload conditions. A temperature responsive load current sensing network is employed to maintain the peak available power supply output current constant, and a constant potential source is utilized for the foldback circuitry to render the foldback characteristic independent of line voltage variations.

Logic functions for magnetic bubble devices

Abstract: An analysis has been made of the number and types of logical functions which can be performed using the interaction of circular magnetic domains in rare earth iron oxides. Multiple logic functions are found to be produced simultaneously at any logical area. These conjunctive output sets have been categorized. Several conjunctive logic gates have been designed, fabricated, and tested successfully in Sm 0.55 Tb 0.45 FeO 3 using Permalloy overlays. Utilizing a circuit in which AND/OR logic gates are coupled to a dynamic memory bank, the total correlation of two data streams has been performed. It is shown how this multiply accessed dynamic memory serves to establish the correlation threshold.

Interface circuit for coupling bipolar to field effect transistors

Abstract: Bipolar and field effect transistors have different threshold voltage and different voltage swings during operation, and furthermore, the threshold voltage for a field effect transistor may be unpredictable when the field effect transistor is applied to a monolithic IC chip. A circuit is disclosed whereby the output of a bipolar transistor circuit such as a logic circuit may drive the input of a large scale integrated field effect transistor circuit, which may involve other logic circuits.

Digital sorter and ranker

Abstract: A digital sorter and ranker in which pairs of binary words are subtracted from each other in adders by feed-in in one word of the pair together with the adjacent word one''s complement. A carry output indicates which word is the lowest and this output is fed through coincidence logic circuits to additional series of address and logic circuits in pyramid fashion until a single output is obtained from a final adder. The adder logic circuits, the carry output and the output of the final adder are fed through minimum value logic circuits to a series of minimum value flip-flops with the outputs thereof being fed back to the adders and their logic circuits. To record the rank of each word, a series of flip-flop groups with each group corresponding to a binary word is set according to the word''s rank, the flip-flops being controlled by gating circuits fed by preceding logic circuits, the final adder, and a binary counter.

Basic ternary logic circuits

Abstract: Basic ternary logic circuits provide all 27 single-variable ternary logic functions. Each of two current switches comprises a pair of transistors. Each transistor has an emitter connected to a respective one of a pair of current sources. The collector of one transistor of each current switch is connected to a load impedance and the collector of the other transistor is connected to a power supply. The input is at the base of one of the current switch transistors. The signal at the junction of the load impedance and the collectors is transmitted to the output by an emitter follower.

High voltage pulser circuit for driving row-column conductor arrays of a gas discharge display capable of being made in integrated circuit form

Abstract: There is disclosed an interfacing system for driving row-column conductor arrays to the gas discharge display panel in a low cost integrated circuit assembly. Due to the requirement of opposite polarity or bidirectional signals being applied to the conductors in the arrays, although the integrated circuits are functionally identical in translating low level logic signals to relatively high voltage (150 volts) pulse signals which are algebraically added to sustainer voltages, one of the circuits includes as a part of the logic circuit an inverting transistor; and to reduce current loading by the logic circuit on external data sources and at the same time serve as a part of a logic gate; and the high voltage switching circuits include a feedback diode for enhancing the response time.

Full-power/half-power logic gate

Abstract: An integrated circuit logic gate suitable for use in LSI arrays provides OR and NOR logic outputs and includes additional collector and emitter resistors causing the array to be operated at half power levels. If a full power array is desired optional metalization shunting of the additional emitter and collector resistors is provided while maintaining the full logic swing across the same DC reference level which exists for half power operation. Thus, full power and half power gates may be interconnected without necessitating the use of additional interface circuits.

Clamping arrangement for reducing the effects of noise in field effect transistor logic circuits

Abstract: A field effect transistor logic circuit includes two seriesconnected field effect transistors forming a shunt path connected between an input node on which noise voltage levels may appear and a reference voltage level. Conduction of one transistor is controlled by a recurring clock signal while the other transistor is rendered conductive by precharge circuitry responsive to the logic level of the input voltage at the input node. For an input voltage having a logic level corresponding to the reference voltage level (e.g., electrical ground), both transistors in the shunt path are rendered conductive and any noise on the input node is shunted to the reference voltage level. Overall circuit operation is controlled by two, double-width clock signals having a phase separation therebetween.

Control logic for switching rectifier systems

Abstract: In a switching logic for a current controller of the type employing two groups of controlled rectifiers connected in parallel opposition and each arranged for delivering current in a respectively different direction, the logic functions are performed by operational amplifiers or comparators operating as switching elements.

Potential improvements in power-speed performance of digital circuits

Abstract: The characteristics of essentially zero standby power drain, reduced load capacitance, and lower supply voltage of a complementary metal-oxide-semiconductor (CMOS) digital circuit compared with a bipolar transistor circuit offer a potential advantage of 10 to 1000 times in power-speed product.

High speed current-mode logic gate

Abstract: A common-base transistor amplifier in the collector circuit of a current-mode logic gate reduces the Miller effect or multiplication of capacitance between the base and collector of transistors connected to the signal-input terminals. This increases the operating speed and increases the fan-out of the logic gate.

Self-checking combinational logic counter circuit

Abstract: A self-checking combinational logic counter providing three predicted parity change bits. One of the bits is derived by logic independent of the counting logic, the other two bits being derived by logic dependent upon the operation of the counting logic. The three bits are compared to detect a match indicating an accurate prediction of a parity change or retention of original parity.

Compound diffused regions for emitter-coupled logic circuits

Abstract: There is provided a method and apparatus for use in fabrication of emitter-coupled logic circuits in integrated circuit form in which the base regions for transistor-transistor logic transistors and tub regions for emitter resistors for use in these circuits are fabricated utilizing a compound diffusion process. The use of the compound diffusion process both reduces spiking problems prevalent with emitter resistors while at the same time enabling the appropriate doping concentrations in the bases of both the ECL transistors and the TTL transistors to be established by opening up these regions during specified portions of the fabrication process.

Memory drive circuit

Abstract: Floating switch type of memory drive circuit having a transformer with the ends of the secondary winding connected to the base and emitter of a driving transistor TTL NAND logic gates of the type having a pull-up transistor are connected to each end of the primary winding When one of the gates is operated to produce a logic O at its output and the other gate is operated to produce a logic 1 at its output, the driving transistor turns on rapidly When the operating states of the gates are subsequently reversed, the driving transistor turns off rapidly

Logic circuitry for monitoring the cyclic operations of a pair of devices

Abstract: Logic circuitry is utilized to monitor the continued cyclic operation of a pair of devices, e.g., strand feeding devices. As the devices function a pair of trains of pulses are generated and the logic circuit detects and generates a malfunction signal upon the generation of two pulses within one train without the intervening generation of a pulse in the other train. The logic circuit accepts concurrent generation of pulses, and the subsequent reversal of the lead pulse in the trains without the generation of malfunction signals. Facilities are also provided to allow the devices to commence operation independent of control by the logic circuits.

Two phase logic circuit

Abstract: A gate network which permits two levels of logic to be performed by interconnected gate networks which are controlled by the same phase.

Four-phase delay element

Abstract: A four-phase logic delay circuit using two cascaded stages of field-effect transistors where each stage has two cascaded fieldeffect transistors for the storage of logic signals and two additional field-effect transistors for the isolation of the storage field-effect transistors for the duration of two phases of the four-phase signal.

A simple charge regenerator for use with charge-coupled and bucket-brigade shift registers and the design of functional logic arrays

Abstract: A charge-inversion regenerator for use with charge-coupled and bucket-brigade shift registers has been developed. The configuration of this regenerator and its use in functional self-regenerating memory, logic arrays, shift address and control systems will be described.

Threshold logic circuits

Abstract: The invention is a threshold logic circuit including a pair of busses and a plurality of storage-processor elements connected to the busses. Each element is arranged to decide which one of a pair of double-rail input signals has a higher potential and to store the result of that decision. Information read out of storage directs a unit of current alternatively to one or the other of the two busses. A threshold logic adder circuit and a threshold logic two''scomplement circuit are included.

Computer Optimization of the Transient Response of an ECL Gate

Abstract: A computer program has been developed for the simultaneous optimization of turnon and turnoff in emitter-coupled logic (ECL) logic gates. For given transistor models, the biasing resistors and dc voltage source values are automatically adjusted such that the actual response is as close as possible to the desired response.

Development of an ECL gate with a 300 ps propagation delay

Abstract: A beam-lead sealed-junction silicon air-isolated-monolithic (AIM) ECL logic gate is described which has propagation delays of as little as 250 picoseconds. The basic building block of the circuit is a 6 GHz silicon microwave transistor with an f max of 10 GHz. The transistors have 2.5 micron stripes and 2.5 micron spacings with a base width of 0.15 to 0.2 micron. Computer simulations of several popular isolation techniques show that the minimization of parasitics achieved with the AIM technology is necessary to achieve these speeds. The analytically predicted characteristics include a dc transfer slope of 5.1 and the following propagation delays: NOR turn-on: 300 ps, NOR turn-off: 250 ps, OR turn-on: 300ps, and OR turn-off: 410 ps. The differences in the propagation delays are caused by current-source modulation.

Alternating current static control system

Abstract: An alternating current solid state control system utilizing alternating current AND and OR alternating current solid state control logic elements The alternating current logic elements perform their logic functions by comparing the voltage drop across a resistor to a predetermined reference voltage, the voltage drop being caused by the logical input state of the logic element Each element''s output can be used as a feedback to its own inputs or can be connected to the inputs of electrically similar circuits By the use of multiple logical inputs, various feedback connections, and various combinations of the alternating current logic elements complex logic functions can be generated to control mechanical apparatus

Improved logic circuit using a current switch to compensate for signal deterioration

Abstract: An improved logic circuit comprising an input semiconductor, an output semiconductor and a current switch connected therebetween to compensate for signal deterioration in the logic circuit. The input semiconductor is biased to remain unsaturated in response to a binary signal swing at an input terminal. In an AND gate, the input semiconductor is a multi-emitter transistor; in an OR gate, the input semiconductor is a plurality of transistors.

Transistor logic circuits

Abstract: A general purpose transistor logic circuit comprising an AND and an OR stage serially connected in either sequence. Each stage comprises multiemitter input transistor and a single emitter output transistor, the transistors of each stage being of the opposite conductivity type. Each stage provides an emitter follower output to achieve a substantial increase in switching speed and the combined stages effectively cancel voltage shifts occurring across each.

Circuit for performing logic functions

Abstract: This disclosure relates in general to a circuit for performing logic functions, and more in particular to a logic solid-state integrated circuit.

Transistor logic arrangements

Abstract: A nonlinear network is combined with conventional transistor-transistor logic (TTL) circuits to provide an overall arrangement characterized by simplicity, low power dissipation, powerful logic capabilities, high-noise margins and the ability to charge capacitive loads in a high speed manner.

Three-level Gunn-effect logic

Abstract: A three-level Gunn-diode system is studied, which uses positive and negative pulses for the on and off signals respectively. Regenerators and the basic logic circuits (AND, OR, Inverter) have been developed and experimental results are presented.

Sensitivity performance of threshold-logic gates using Chow parameters

Abstract: Existing analyses of the sensitivity of threshold-logic gates to input voltage and component tolerances are, in general, complex. It is here shown that the sensitivity performance of practical gate realisations may be related very simply to the Chow parameters of the gate.