Showing papers on "Pass transistor logic published in 1973"

Low power, high speed, high output voltage fet delay-inverter stage

Abstract: An integrated circuit and a method operating the circuit is disclosed wherein first and second MISFET transistors are connected with the source node of the first common with the drain node of the second and providing the output node of an inverter or delay stage. The output node is capacitively coupled back to the gate of the first transistor. A third transistor also connects the gate of the first transistor to a source of voltage, such as the drain voltage, in such a manner that the first transistor can be controlled and also such that a voltage higher than the drain voltage can be permitted on the gate of the first transistor. The first transistor is turned off and the second turned on to provide a logic ''''0'''' output, and conversely the first on and the seond off to provide a logic ''''1'''' output, with no power consumption in either state. To switch from a logic 0 output to a logic 1 output, the first transistor is switched on just prior to the time the second is being switched off so that as a result, the gate of the first transistor is ''''bootstrapped'''' to a voltage in excess of the drain voltage as a result of being capacitively coupled to the output node as the second transistor is switched off. The very high gate voltage results in very rapid switching of the first transistor to an output level equal to the drain voltage, yet results in excess power consumption only during the short switching cycle while both transistors are on. The same results can be achieved without using the second transistor if the gate node of the first transistor is switched on very rapidly. The circuit third transistor is switched on very rapidly. The circuit can be used as a delay stage for clock generators or as an inverter stage, depending upon the node selected as the data input.

Logic circuit arrangement employing insulated gate field effect transistors

Abstract: A logic circuit arrangement consisting of insulated gate field effect transistors of opposite channel types wherein the drain electrode of a single first insulated gate field effect transistor of one channel type is connected to the drain electrode of at least one second insulated gate field effect transistor of the opposite channel type constituting a logic gate. The gate electrode of second transistor is supplied with a data signal and the gate electrode of first transistor and the source electrode of second transistor are supplied with clock pulse signals bearing a complementary relationship with each other. The source electrode of first transistor may receive a clock pulse signal supplied to the source electrode of second transistor or constant voltage; and an output signal from the logic circuit is delivered from the junction of the first and second transistors.

Integrated circuits in digital electronics

Abstract: Perspective Number Systems Switching Functions Combinational Logic Logic Gates Latches and Flip-Flops Sequential Circuits Arithmetic Circuits Coding, Code Conversion, and Error Detection and Correction Digital-to-Analog and Analog-to-Digital Converters LSI and VLSI Practical Considerations Index

Emitter function logic-logic family for LSI

Abstract: A highly efficient large-scale integration logic family combining the advantages of multiemitter structures with the performance of emitter-coupled logic is discussed. Simplified gate structure has been found to reduce propagation delay, power and number of logic levels required for logic function realization. Conventional processing affords 2-5-pJ performance. The principle of operation of a basic AND-OR gate is shown and compared with the well known ECL gate. Fundamental gating and sequential logic functions are compared with the conventional inverting designs. The solid-state realization of a test gate is described. The speed-power performance advantage of emitter function logic gates and functions are contrasted with those of presently popular logic families.

Subnanosecond emitter-coupled logic gate circuit using Isoplanar II

Abstract: Describes a 650-ps propagation delay voltage and temperature compensated emitter-coupled logic dual-gate circuit using a new and significantly improved transistor structure. The transistor structure is an improvement over standard Isoplanar and is called Isoplanar II. Isoplanar II transistors eliminate the need for base region diffusion beyond the emitter ends, and for a given emitter size the collector-base junction area is less than 40 percent of the area otherwise needed for the conventional Planar transistor. The total silicon area per transistor is reduced by more than a factor of 2 over conventional IC techniques. These features reduce the collector-base and collector-isolation capacitances significantly. The result is significant improvement in switching performance without any sacrifice in voltage levels and voltage supply tolerances.

Comparison of MOSFET logic circuits

Abstract: Linear load, depletion-mode load, four-phase dynamic, and complementary MOSFET logic circuits are compared on the basis of power, delay, and density for two specific master slice layouts. The circuits were designed in a common technology base, and normalized power and delay characteristics were calculated by simulation. Chips of 1280 circuits were designed in images having one and two layers of metal, and power versus delay curves were calculated. The effect of an insulating substrate was also considered.

Digital-summation threshold-logic gates: a new circuit element

Abstract: Threshold-logic gates are memoryless, multiple-binary-input single-binary-output circuits that operate by an arithmetic summation process to determine the 0 or 1 gate output state The availability of such gates would be of great advantage to digitial system design A new approach to the circuit realisation of such gates is presented here, ie to use digital-summation techniques within the gate circuitry, as distinct from the analogue-summation techniques previously employed The adoption of digital summation removes the former circuit-tolerance problems, and allows gates with great potential usefulness to be readily designed

Emitter coupled logic transistor circuit

Abstract: In an emitter coupled logic transistor circuit, a plurality of data gates are arranged for multiplexing input data onto a common output means in response to a coded multiplex signal which selects respective data gates sequentially. A common current source is connected to respective ones of said data gates via the intermediary of respective current switch gates, such current switch gates being responsive to the decoded input select command signals for selectively energizing respective ones of said data gates, whereby power consumed by the multiplex circuit is minimized since only a selected data gate is powered up at any given time.

Fully-compensated emitter-coupled logic: Eliminating the drawbacks of conventional ECL

Abstract: New approaches to high-speed emitter-coupled logic circuitry, overcoming system drawbacks by eliminating sensitivity to environmental changes, are discussed. A comparison is made with uncompensated conventional ECL. Circuits displaying threshold and level invariance over wide ranges of ambient temperature, typically greater than 0/spl deg/-75/spl deg/C, and supply voltage, -4.7 to -6.2 V, are described. Suggestions are made as to how these features can lead to higher performance, and at the same time, lower cost systems.

Flip-flop circuits utilizing insulated gate field effect transistors

Abstract: A flip-flop circuit utilizing insulated gate field effect transistors or MOS transistors and operating as a set dominant type or a reset dominant type includes a delayed logic circuitry having a three-input logic circuit comprised of an AND-NOR gate constituted by P and N channel MOS transistors, and P and N channel clocked MOS transistors for operating the logic circuit in synchronism with a clock signal and a complement thereof. The output of the delayed logic circuitry is reversed in polarity by a first complementary MOS inverter. The three-input logic circuit receives a first logical input through a second complementary MOS inverter, a second logical input, and the output of the flip-flop circuit.

Oxide-isolated monolithic technology and applications

Abstract: Describes the use of selective oxidation and ion implantation to fabricate integrated circuits. The technique of selective oxidation is used to fabricate a `walled emitter' structure as proposed by Panousis. This allows a substantial reduction in transistor size, for a given active area, over standard fabrication techniques. At the same time, parasitic device capacitances are reduced and a considerable improvement in circuit performance is realized. The impurity distribution in the various components is established by the extensive use of ion implantation. It has been demonstrated, experimentally, a 30-pJ resistor transistor-transistor logic gate fabricated using the collector diffusion isolation technology, can be fabricated in oxide isolated monolithic technology with a power-delay product of 6 pJ. Current-mode logic gates have been fabricated with a power-delay product of 1 pJ.

Complementary dynamic m.o.s. logic circuits

Abstract: Allowing both p and n channel groups of transistors to be blocked between transitions of c.m.o.s. gates leads to complementary dynamic m.o.s. circuits which, in many cases, are significantly less complex than their static counterparts. The value of the concept and a method of synthesis are demonstrated with a practical example. Systematic application to frequency dividers yields very simple new structures.

Logic circuit arrangement using insulated gate field effect transistors

Abstract: A logic circuit arrangement includes a first transistor having the source-drain conduction path connected between a first power source terminal and an output point and rendered conductive in response to a clock pulse applied to the gate electrode, and a plurality of second transistors, constituting at least one logic gate, each having the source-drain conduction path connected between the output point and a second power source terminal and the gate electrode supplied with a logic input. The arrangement is such that current is not concurrently flowed between the first power source terminal and the output point and between the output point and the second power source terminal. The source-drain conduction path of a third transistor is further connected between the first power source terminal and a junction of the adjacent two transistors in the logic gate and rendered conductive, during the conduction of the first transistor, in response to a clock signal applied to the gate electrode, so that a voltage of the output point indicates a predetermined level corresponding to a logic ''''1'''' or ''''0'''' irrespective of the difference of operation mode of each transistor.

MultiFunction Threshold Gates

Abstract: Threshold logic gates, up to now, generally have been presumed to provide a single function of the input variables. The threshold gates that have been integrated [1]-4] were naturally double-sided and provided complementary outputs or, more specifically, complemented dual outputs. This paper shows that the inphase and out-of-phase outputs can, in fact, be designed to provide grossly different functions of the input variables. Two examples of this technique have already been shown [5] and one of these, the full adder, has been demonstrated in a multiplier [6]. Now this technique is generalized, and furthermore, it is shown how each side can be subdivided to provide a number of functions simultaneously. Finally, virtual oRing of specific output points from each side will result in still more functions. The sum-resistor specification for any order function on either side is given. Practical application of these techniques are discussed, including those basic ones that have already been disclosed.

EFL logic family for LSI

Abstract: A highly-efficient LSI logic family combining the advantages of multi-emitter structures with the performance of ECL logic will be discussed. Simplified gate structure has been found to reduce propagation delay, power and number of logic levels required for logic function realization. Conventional processing affords 2-5 pJ performance.

Adaptive logic circuits for digital stochastic computers

Abstract: A theoretical and experimental investigation of adaptive logic elements suitable for use as an output interface for digital stochastic computers is presented. An adaptive digital element using a binary rate multiplier is demonstrated to provide a significant improvement in accuracy without reduction in bandwidth characteristics.

Two-phase dynamic logic circuit

Abstract: A two-phase dynamic logic circuit comprises first, second, and third MOS transistors and a logic means which includes an input terminal and an output terminal. The drain of the first transistor is connected to a D.C. voltage or to the first clock signal source and the gate of that transistor as well as the drain of the third transistor are connected to the first clock signal source. The sources of the first and second transistors are connected to the output terminal of the logic means. The gate of the second transistor is connected to the second clock signal source, and the drain of that transistor is connected to the gate of the third transistor. The output signal of the circuit is derived from the source of the third transistor.

Process for stress testing FET gates without the use of test patterns

Abstract: A testing process is described for stress testing each gate electrode in a dynamic random logic FET circuit array incorporated in an LSI device. The process comprises the steps of providing operating potentials and clock signals to each logic circuit in a logic path in the LSI device; providing a stress voltage to each initial logic element in a logic path, and sequencing the clock signals to each logic circuit in reverse order to that sequence required to transfer information through a logic path to perform the circuit logic function. The invention advantageously utilizes the fact a reverse clock will sequentially stress each logic circuit while in a discharge state and the other logic circuits are in a non-conducting condition.

Logic circuit having common load element

Abstract: A logic circuit comprises a first logic block composed of one or more metal-insulator-semiconductor field-effect transistors (MISFETs), a second logic block composed of one or more MISFETs, and a transfer gate MISFET adapted to be turned on and off between the first and second logic blocks: Current control MISFETs are connected in series with the respective logic blocks and driven by clock pulses differing in phase so as to prevent the current control elements from coincidentally turning on, and a load MISFET is commonly connected to the first and second logic circuit.

Logic circuit using a current switch to compensate for signal deterioration

Abstract: An improved logic circuit comprising an input semiconductor, an output semiconductor and a current switch connected therebetween to compensate for signal deterioration in the logic circuit. The input semiconductor is biased to remain unsaturated in response to a binary signal swing at an input terminal. In an AND gate, the input semiconductor is a multi-emitter transistor; in an OR gate, the input semiconductor is a plurality of transistors.

Field effect transistor logic gate with improved noise margins

Abstract: The noise margins of a standard field effect transistor logic gate circuit, connected between first and second logic potential terminals, are substantially unequal because the transition region between logic states typically occurs much closer to the more positive of the two potentials. Significant improvement is achieved by detaching the connection to the more positive terminal of the standard logic gate circuit and attaching it to the center tap of a second circuit, comprising a series connection of two additional field effect transistors. The second circuit, connected between the first and second potential terminals, forms a voltage divider and a continuous current path. The respective control electrodes of the two additional transistors are jointly connected to the less positive of the two terminals, causing one of the additional transistors to operate in its triode region and the other to operate in its saturation region. The transition region of the logic gate circuit is thereby narrowed and approximately centered between the two potentials.

Four-phase logic systems

Abstract: A four-phase logic system is provided which includes at least four logic networks connected in parallel between a single power line and a reference potential. A four-phase clock generator generates four distinct clock signals from a single-phase clock input at data rate. Each logic network comprises a pair of complementary metal-oxide-semiconductor integrated transistors (CMOST). Each metal-oxide-semiconductor transistor (MOST) in the pair is responsive to a clock signal which turns the transistor ON or OFF. In each network there is also at least one MOST which is responsive to a logic signal. The logic transistor is connected in cascade with the pair of CMOSTs. A stray capacitance which serves as a storage capacitor between the junction of the pair of transistors and a reference potential provides an output signal dependent upon the applied clock signals and the incoming logic signal.

Full adder and subtractor circuit

Abstract: A full adder and subtractor circuit comprises four logic units, wherein a first logic unit carries out a logic operation on first and second operands and on information of a preceding bit to provide an output of carry information; a second logic unit carries out a logic operation on said first and second operands, said information of the preceding bit and said output of the carry information providing a result of an arithmatic operation on the first and second operands; a third logic unit carries out a logic operation on the second operand, the output of the carry information and the information of the preceding bit providing an output of a borrow information, and a fourth logic unit carries out a logic operation on an operation instruction, the output of the carry information and said output of the borrow information providing information of a succeeding bit.

Dynamic logic interconnection

Abstract: A dynamic logic interconnection comprises a plurality of individual logic circuits connected in series, the individual logic circuits including a diode element in series with the controlled current path of an active circuit element, to which individual circuits single phase clock pulses are applied at the same time.

Logic detector apparatus

Abstract: Logic detector apparatus for detecting positive and negative voltage levels with respect to ''''one'''' and ''''zero'''' reference levels in either positive or negative logic modes the apparatus including a NOR gate output stage coupled to the outputs of four selection NOR gates, respective selection NOR gates being associated respectively with detecting positive and negative voltage levels with respect to the reference levels in positive and negative logic modes, and a comparator for detecting positive and negative voltage levels, the output of the comparator being coupled to the selection NOR gates, whereby respective selected NOR gates control the output of the output NOR gate to provide respective outputs responsive to whether the logic signal detected is more or less positive than the respective ''''zero'''' or ''''one'''' reference level in either logic mode.

Superintegrated voltage clamp

Abstract: A monolithic implementation of a voltage clamp circuit is described that saves area and reduces capacitance, as the transistor and the voltage divider resistor required are merged into a single device Following this principle in current switch logic circuits, even the emitter follower can be superintegrated into the collector loads Moreover, base-bleeding resistors can be incorporated in transistors of silicon-controlled rectifiers

Transistor-transistor logic circuitry and bias circuit

Abstract: An improved modified transistor-transistor logic (T2L) circuit having operating voltage compatible with existing T2L logic blocks which includes a coupling transistor having its base connected to a current source and being selectively responsive to switch current either between its respective base emitter terminals or base collector terminals, and an output transistor having its base connected to the collector of the coupling transistor for generating an output signal at its collector terminal, and an on diode connected to the emitter of the output transistor for providing a current path constituted by the base-to-collector terminals of the coupling transistor, the base-to-emitter terminals of the output transistor, and the on diode. The modified T2L circuit is also compatible with a lower power supply voltage source.

Design and application of a modified universal logic module

Abstract: The basic concept of an n-variable universal logic module (ULM-n) as developed by Yau and Tang is extended so that the input control functions are simple two-bit binary codes and not determined by one of the n variables. Although the resulting design is not a minimum pin configuration, it has the advantage that the control variables are 0 and 1. Basic ULM-2 and ULM-3 are developed and a method of using them to implement higher variable ULM's is also considered.