Showing papers on "Reading (computer) published in 1980"

Method, apparatus and record carrier body for optically writing information

Abstract: Disclosed is a method and apparatus for recording information on a disc-shaped record carrier body with a single beam of radiation The record carrier body is provided with a servo track which preferably exhibits a phase structure and which contains a multitude of sector addresses each associated with a portion provided with a radiation sensitive layer Before the information is recorded, the beam is switched to a low, read level and the desired address is located Simultaneously, the radial position and tangential speed of the radiation spot and the focusing of the radiation beam are checked Once the desired address is located, the beam is switched to a higher, write intensity and the information is recorded on the radiation sensitive layer of the portion associated with that address During recording, the radiation returning from the record carrier can be used to check whether the information is recorded correctly During reading of the recorded information, the servo track may be used for positioning the radiation spot on the information track

Wand turn-on control

Abstract: Disclosed is a control circuit used to conserve power in a portable optical recognition system. When the system is not being used or between actual scans of the reading electronics, power is supplied only to those circuits required to control power to the system and to permit sequence reading of items. An infrared signal is emitted from the reading device and when a document or other item to be read is scanned the infrared signal is reflected back into the scan unit and is detected, thereby sensing that a document is being read and turning the system on.

Semiconductor memory device test apparatus

Abstract: A memory device under test is accessed by an address generated by a pattern generator to write therein data and to read the data out to be compared with expected data, and the comparison result is stored in the fault-address memory by the same address after reading out therefrom the content of the address. When a disagreement is detected through the comparison, it is counted; however, the count operation is inhibited if the data read out from the fault-address memory is a fault data. When the counted number exceeds a predetermined value, a fault signal is generated. After the test is terminated, an address counter is operated, the fault-address memory is read out by the content of the address counter, and when fault data is detected from the output read out, the content of the address counter is fetched into the CPU.

Document data filing/retrieval system

Abstract: A document data filing system used with an index data list bearing the index data associated with the document data on a plurality of documents, comprises read means for reading the document data on the document and the associated index data on the index data list, a first buffer memory for temporarily storing the document data read out by the read means, a second buffer memory means for temporarily storing the index data read by the read means, and a memory control means for applying the document data stored in the first buffer memory, together with the corresponding index data stored in the second buffer memory

Cooking assistance device and a combination thereof with a microwave oven

Abstract: A cooking assistance device for use with a microwave oven comprising a card reader for reading a menu data recorded in a card, a memory unit in which data representing the quantity of foodstuff materials to be heated by said oven and heating processes are stored, and a control unit for reading data from said memory unit in response to the menu data. A character code generator provides conversion of the data read from said memory unit into a character code which is fed into a mini-printer mounted in said oven to provide a print out of characters on a recording medium. A data input key is also provided for entry or alteration of data representing the quantity of servings. A power controller determines the power level and heating interval of the foodstuff based on the stored and keyboard input data and accordingly controls the heating operation.

Nonvolatile semiconductor memory

Abstract: PURPOSE:To attain high density and low power consumption of a nonvolatile semiconductor memory by forming a memory of an impurity region, an insulating layer, and an electrode layer or the like, constituted in a prescribed way on a substrate, and reading dynamically the stored electric charge. CONSTITUTION:An n-channel 1st impurity region 121 and the 2nd impurity region 122 used as a bit line are provided on a p type silicon substrate 11 and a selection electrode layer 14 used as a word line is formed between the regions 121 and 122 via a gate oxide film 13. On the other hand, a control gate electrode layer 19 or the like via a gate oxide film 15, field oxide film 16, floating gate electrode layer 17 and a poly silicon oxide film 18 in constant with the region 121 is laminated to form the nonvolatile semiconductor memory. Through the constitution above, the presence of an electric charge of the layer 17 is read by the dynamic detection of a charge amount stored in a capacitor made of the layer 17 and the substrate 11, the source region of a storing transistor, its wiring and a decoder or the like are not required and the high density and low power consumption of the nonvolatile semiconductor memory are attained.

Buffer memory referencing system for two data words

Abstract: A memory accessing system for reading or writing consecutive addressable words is described for use in a set associative memory system. Two high speed buffer memories store words read in blocks from a slower main memory. One buffer stores even addressed words and the other stores odd addressed words. Each buffer memory has a tag memory associated with it for indicating data words stored in the buffer memories. A comparison circuit compares two addresses to be accessed to the tags and provides hit or miss signals for each address indicating residency or non-residency in the buffers. If both addressed words are resident, access to read or write the two consecutive data words is accomplished simultaneously. If either or both addressed words are not resident in the buffers, the main memory is accessed to acquire a block or blocks containing the missing addressed word or words. Consecutively addressed data words can occur within a block or across block boundary. The system examines the addresses and gives an indication when a block boundary crossing is to occur, and provides accessing to read or write sequentially addressed data words across the block boundary crossing simultaneously.

Device for reading a printed code and for converting this code into an audio signal

Abstract: A carrier containing information which is suitable for visual perception, such as a text or a picture. By suitable positioning, a code also present on the carrier linked thereto. This code is visible to the user, but cannot be read directly. A device for reading the code having a scanner which can be moved into the area of the code by hand. The code is optically read, synchronization signals being obtained from the code itself. The information read is stored in an intermediate memory. The intermediate memory is subsequently read under the control of a clock. This data can either directly activate an acoustic generator for producing a sound signal, or can address an object memory which in its turn supplies data for controlling the acoustic generator. A sound signal is thus linked to the picture or the text. A device of this kind may form part of an educational system.

Video recording on disk and device for the repetitive reading of such a recording

Abstract: The invention relates to recordings in the form of disks and to the reading devices making it possible to repetitively read a still with its sound accompaniment. The invention relates to a recording where the video and audio data form interlaced blocks located in equal sectors of the same turn. The repetitive reading device utilizes buffer stores in which are loaded the video and audio data blocks. The reading of the buffer stores takes place at a reduced speed in order to reconstitute uninterrupted sequences of video and audio data. The invention is more particularly applicable to the storage of pictures on disk with their sound accompaniment with a view, for example, of giving programmed audio-visual instruction or teaching.

Variable delay circuit for emulating word line delay

Abstract: A semiconductor memory having an address buffer (10), row decoder (12), word lines (16), bit line (20) and sense amplifier (22) for accessing individual memory cells in an array of memory cells. In order to emulate worst case delays experienced in the word lines in accessing the last cells in the rows in order to prevent the sense amplifiers (22) from reading the bit lines (20) too soon, a tunable delay circuit (30) delays actuation of the sense amplifier. This circuit is divided into a plurality of impedance section with associated parasitic capacitance where groups of sections are bypassed by switching devices such as MOS transistors. The delay of a signal propagating through this tunable delay circuit can be varied by bypassing varying numbers of the sections with the switching devices.

High speed data interface buffer for digitally controlled electron beam exposure system

Abstract: An electron beam exposure system for forming integrated circuit patterns in which pattern data provided by either a control processor or a mass storage device is transferred through a pattern buffer interface which contains a large buffer memory, the reading and writing of which is automatically controlled by read and write logic contained within the interface. Data is transferred to the interface over busses having a data width less than the data width capable of being stored at an addressable location in the buffer memory. Automatic assembly of larger units of data is controlled by logic within the interface which requires only initialization by the control processor. Automatic address sequencing for subsequent data transfers is carried out under control of self-incrementing storage address registers and self-decrementing word count registers. Transfers of data to the electron beam column, through a pattern generator, is provided in addressable data units, while transfers to the control processor or mass storage device are provided as sub-units of an addressable data unit compatable with their respective buss widths.

Electronic calculation/memorandum apparatus

Abstract: An electronic calculation/memorandum apparatus comprises: a main memory; a key input unit including character keys, numerical keys, symbol keys, and a character mode selection key, a data write-in key for the main memory, and a data read-out key for the main memory; means for setting the main memory to a write mode through the operation of the write-in key; means for writing index data including characters and/or symbols inputted from the key input unit and numerical data associated with the index data in the order of inputting of them into the input key, into the main memory successively from the head address and the succeeding ones; means for alternately reading out all the index data and numerical data stored in the main memory in the order of the writing thereof in the read-out mode and for displaying them; means for retrieving the numerical data corresponding to the index data inputted from the main memory and for displaying it; and a unit for performing calculation on the basis of numerical data inputted through the operation of the numerical key.

Resynchronizing circuit for time division multiplex system

Abstract: The invention relates to input and output circuits for multiplexing equipment, especially the kind used in telephone systems where nominally identical clocking signals have natural deviations of timing (called "plesiochronous" signals). The invention uses the "justification" principle to ensure the clock synchronization of plesiochronous digital signals. A buffer memory, with independent writing and reading capabilities, is formed of two first in-first out or "FiFo" memories connected in series. The request signal for a "justification" is made when a connection is completed between an IR (Input-Ready) output of the second FiFo memory and an input SO (Shift-Out) of the first FiFo memory, if there is an undesirable phase shift between the input and output clocking system. A reading clock oscillator has a frequency which is governed by a governing signal, which depends, at least in part, upon the electrical state existing in the series connection between the IR output of the second FiFo memory and the input SO of the first FiFo memory. The receiving and demultiplexing system uses a similar buffer memory to extract any "justification" signals which were added on transmission. A phase-locked loop including a quartz-controlled oscillator controls the output clocking of the demultiplexer.

Dot matrix printer with compressed character data storage

Abstract: A method and apparatus for performing dot matrix printing in which the storage capacity of a memory used for storing character patterns is significantly reduced and the accompanying decoding process is quite simple. Character patterns to be printed are coded in patterns of normal and half-shifted dots, and data representing both types of dots is stored in a read only memory. Half-shift instructions are stored in the memory to identify which dots are to be printed at half-shifted positions located between adjacent columns in a matrix used as a reference from which the character pattern is encoded. Several half-shift instructions are stored for each row with each instruction corresponding to a plurality of adjacent dot locations in the associated row. In reading out data from the memory, each half-shift instruction is effective until the location of the next half-shift instruction is reached. In a preferred embodiment, the character patterns are encoded so that the memory can be read bi-directionally, printing in two directions.

Apparatus and method for controlling electronic controlled cooking apparatus having storage

Abstract: A microwave oven including a keyboard, a microwave generating circuit, and a microprocessor for controlling the same. The keyboard has function keys for setting cooking conditions, numeral keys, and a memory key for commanding storage and retrieval of cooking information from a random access memory. The microprocessor is responsive to an operation of the memory key to transfer cooking information set by the function keys and numeral keys, from a buffer memory to a particular storing stage of the random access memory, according to the setting of a number of flag bits in the buffer memory. New cooking information is then transferred to the buffer memory from the next storing stage of the random access memory, and the flag bits are reset to indicate which storing stage corresponds to this information. The cooking and stage identifying information in buffer memory is read out by a display, and the displayed cooking information may be changed without affecting the content of the other storing stages in the random access memory.

Record operated control system for a vending machine

Abstract: A record operated control system is provided for use with a vending machine and a record reading/writing apparatus having a read/write head for reading and writing data on a record during relative movement between the record and the read/write head. The control system includes a decoding circuit coupled with the read/write head for decoding data read from the record thereby. A data storage circuit is coupled with the decoding circuit for receiving and storing the decoded data. A comparing circuit compares at least a portion of the stored data to predetermined data and produces a compare signal if these data compare. A data altering circuit is responsive to the compare signal for altering the stored data in accordance with the amount of credit required to vend a selected item. An encoding circuit is coupled with the storage circuit and with the read/write head for causing writing of the altered stored data onto the record. A vend enable circuit is responsive to the compare signal and to the altering circuit and said encoding circuit for enabling the vending of said selected item only after the altering and writing of the stored data. A control circuit controls the sequence of operation of the control system in the foregoing sequence.

Unidirectional data transmission system

Abstract: A system broadcasts videotext data in the form of data packets originating from numerical data coming from several paths. Each packet has a prefix which contains synchronization and path identification code signals, a format signal which indicates the length of the data which follow the prefix. The transmitting station has as many coupling devices as there are paths for originating data. The coupling device has a data memory coupled to drive to a multiplexing circuit under the control of a common governing circuit. An inhibition order is given either as soon as the memory is full, or as soon as a counter has reached a pre-determined count. Then, the memory is connected to the multiplexing circuit, into which the stored data is emptied. The system is characterized in that a small capacity buffer is used between the memory and the input circuit for reading data out of the buffer memory responsive to a programmer. A transcoder treats the broadcast data to fit it into the system format.

Liquid level recorder apparatus and method for storing level differences in memory

Abstract: A shaft position recorder apparatus and method are described which can be used for recording changes in liquid levels. The recorder employs an electronic memory for storing the changes in liquid levels which are entered into the memory at predetermined time intervals if they exceed a predetermined magnitude or "deadband". The recorder apparatus employs a shaft position encoder as an input means for supplying a group of pulses for each measured change in shaft position or liquid level so that the sequence of the pulses indicates whether the change was an increase or decrease from the previous reading. The preferred shaft encoder includes three reed switches which are operated by four permanent magnets mounted on a support disk which rotates in accordance with the position of the shaft, such shaft being coupled to a float pulley when used as a liquid level recorder. The reed switches are closed in different sequences when the support disk is rotated in opposite directions to produce the groups of pulses on three parallel outputs connected to a computer for analysis to determine if level change is up or down; and to produce a present level signal. The recorder contains a temporary or scratch pad memory which stores a datum reference signal corresponding to the previously measured liquid level signal. This datum reference signal is compared with the present level signal to produce a difference level signal corresponding to the differences in their amplitude which is then compared with a predetermined deadband limit signal to produce an output difference level signal when it exceeds such deadband. The output difference level singal is periodically gated every 15 minutes to a permanent memory where it is stored and is also transmitted to the datum memory to update the datum reference signal. In addition, the recorder includes a maximum level memory and minimum level memory which continuously monitor the present level signal, temporarily store and transmit maximum and minimum level signals through gates to the permanent memory at the end of a predetermined time period such as every 24 hours.

Method of fabricating random access memory device

Abstract: A dynamic random access memory is fabricated on a monolithic chip of semiconductor material. The memory is formed of an array of memory cells controlled for reading and writing by word and bit lines which are selectively connected to the cells. Each cell is a single field effect transistor structure having improved electrical charge storage capability. The improved charge storage capability of each cell is provided by an electrical capacitance structure uniquely arranged and formed as an integral portion of the field effect transistor structure. The gate electrode of each field effect transistor structure is connected to a predetermined one of said word lines. The drain of each field effect transistor is connected to a predetermined one of said bit lines. The source of each field effect transistor structure is integrally connected to and forms a portion of the uniquely arranged electrical capacitance structure of the field effect transistor structure. The electrical capacitance or storage node structure of each cell has increased electrical charge storage capacity and may be considered as a single capacitor. The single (storage) capacitor of each cell is provided between the source of the field effect transistor, a source of reference potential (reference plane) and the monolithic semiconductor substrate on which the memory is fabricated. The arrangement of the memory cells, the structure and material of each of the memory cells, and a method of fabricating the entire memory is disclosed. Also disclosed is an improved field effect transistor structure and process for fabricating same. The process of fabrication, cell arrangement and the improved storage node of each memory cell, as structurally fabricated and uniquely arranged, provides a monolithic memory having improved density and operating characteristics.

Organization for dynamic random access memory

Abstract: An MOS dynamic random access memory (RAM) includes an array of memory cells arranged in rows and columns. The array is divided into two or more sub-arrays (1001, 1002). In an operating cycle where a cell is being accessed for reading and/or writing, only the sub-array containing the accessed cell is fully selected while the other sub-arrays are partially selected. A fully selected sub-array is one in which both a row and a column are selected, whereas in a partially selected sub-array, only a row is selected. In the partially selected sub-array where only refreshing of the cells in the selected row takes place, the column (1003, 1004) decoders and drivers remain inactive throughout the memory cycle.

Optical information reader

Abstract: PURPOSE:To enable to read in the bar code of read-in body fed in any angle without misreading, by reading in the bar code while one dimension photo diode array is moved parallelly. CONSTITUTION:The self-scanning type primary dimension photo diode arrya 1 is located within the read-in body image forming plane 6 where the image of read-in object 3 is formed with the lens 2, and the array 1 can be moved left and right with the rod 7 of the rotary board 5 coupled with the motor 4. Further, the moving speed of the array 1 is sufficiently made faster than the moving speed of the read-in body 3, and while the array 1 moves from the right end sensor 9 to the left end sensor 8, the signal is photo electric conversion on the image forming plane is sequentially read out with the self scanning. After it is converted into digital signal at the sample hold amplifier 11, it is stored in the memory 13. The content stored in the memory 13 is sequentially read out with the control of the ROM 16 and the control circuit 14 assembling the program processed in advance and the bar code is read in, allowing to read in the bar code of the read-in body 3 fed with any angle.

Method of preparing and executing sequence program for sequence controller used in machine tool control

Abstract: A method of preparing and executing a sequence program for effecting the sequence control of a sequence controller for a machine tool by executing a subroutine program. A sequence diagram is prepared, which diagram expresses a function command for a subroutine as data divided into control conditions and parameters. From the sequence diagram a sequence program is prepared, which program includes a command for reading data indicative of a control condition, and parameter data of which a subroutine is informed. The sequence program so prepared is then executed.

Data processing system

Abstract: PURPOSE:To increase a processing speed and to improve reliability by digitizing a periodical input signal and dividing a data holding time into two parts to execute writing and reading cycles respectively. CONSTITUTION:A periodical signal is digitized by a voltage comparator 10 and a latch FF12 and data are divided into the 1st data system obtained by alternately selecting data an the 2nd data system consisting of remaining data. When a writing clock is inputted to a writing address counter 16 and writing address data are supplied to a RAM14 through an AND circuit 18 and an OR circuit 20, data in respective systems are written in respective areas independently at real time band. Then, a reading clock having a prescribed frequency is inputted to a reading clock counter 22 and reading address data are supplied to the RAM14 through an AND circuit 24 and an OR circuit 20. The data are individually read out from respective areas at the time band having length corresponding to an integer ratio to the real time band and at least partially overlapped to the data writing time band and the data of respective systems are combined.

Time slot multiplex system for the division multiplexing of digital communication signals

Abstract: A time slot multiplex device for a time division multiplex system having a voice memory for storing data words received on an input multiplex line, and a control memory for controlling the reading of said voice memory to an output multiplex line, incorporates logic circuitry for generating a plurality of associated pairs of addresses, one for said control memory and one for said voice memory, corresponding to a plurality of equally spaced time slots for a multi-channel connection to said output multiplex line of relatively high band width, in response to a single pair of associated addresses furnished by a higher ranking control means and a logic circuit which, in association with a time slot counter, generates the required addresses during cycling of the time slot counter through a single frame of the time division multiplex system.

Data string rearrangement unit

Abstract: PURPOSE:To make the rearrangement of high-speed data by a low-speed memory by dispersing and storing a data string on a communication line and then by simultaneously reading, bit by bit, the contents at corresponding addresses from respective memories according to the constitution of a conversion matrix. CONSTITUTION:This unit is equipped with series-parallel converter 11 which converts series input data into parallel data of (m1)-bit words, memory parts #1 to #m2 divided into the (m2)-number memory elements 15 and available for word-by- word writing, and method 14 of writing parallel data to memory elements according to the constitution of rows of the conversion matrix. Further, this is provided with method 18 of reading, bit by bit, the contents of corresponding addresses from respective memory elements at the same time according to the constitution of columns of the conversion matrix, and parallel-series converter 22 which converts the output of the reading method into series data and then outputs it. Consequently, the rearrangement of high-speed data can be performed by the low-speed memory.

A 2Kx8-bit static MOS RAM with a new memory cell structure

Abstract: A 2K/spl times/8-bit static MOS RAM with a new memory cell structure has been developed. The memory cell consists of six devices including four MOSFETs and two memory load resistors. Two load resistors are fabricated in the second-level polysilicon films over the polysilicon gate MOSFET used as the driver. Thus the memory cell area is determined only by the area of four MOSFETs. By applying the new cell structure and photolithography technology of 3 /spl mu/m dimensions, the cell area of 23/spl times/27 /spl mu/m and the chip area of 3.75/spl times/4.19 mm have been realized. The RAM is nonclocked and single 5 V operation. Access time of about 150 ns is obtained at a supply current of 120 mA.

Drain triggered N-channel non-volatile memory

Abstract: An electrically alterable non-volatile memory for storing information is described incorporating an array of memory elements comprising N-channel variable threshold field effect transistors having at times an N-channel extending from its source to a predetermined distance from its drain, means for writing information into the array and means for reading information from the array.

Microprogrammed information processing system having self-checking function

Abstract: An information processing system of the microprogram control type having a control storage is provided with an exclusive memory unit for storing only the address information of a microprogram stored in the control storage and an exclusive control circuit for reading a specific microprogram out of the control storage by the address information from the exclusive memory unit and executing the program read out. The exclusive control circuit operates when the information processing unit is an idle state to execute successively the micro-steps of the specified microprogram read out in accordance with the address information in the exclusive memory unit, thereby to verify the information processing unit.

Bar code reader

Abstract: PURPOSE:To simplify the circuit constitution without using complicated demodulation circuit, by performing read-in through the use of one to one relation between the width comparison data in one character and the bar code pattern, in reading in the bar code pattern of white and black CONSTITUTION:In reading in the bar code pattern consisting of the bar train of white and black, in synchronizing with the clock phi1 of the clock generation circuit producing the clock pulses phi1, phi2 and phi3, the bar and space of the bar code pattern from the read-in and scanning means are corresponded by one to one, and in synchronizing with the front and rear edge of the bar, the control signals CP1 to CP6 are produced The clock pulses phi1, phi2 and phi3 and the control signals CP1 to CP6 are fed to the width comparison circuit providing the counters 213, resister 214 down counters 215, 216 and FF221,222 and comparing the widths between the bar and space to compare the width Further, the width comparison output DN and DW of the comparison circuit is fed to the serial parallel conversion circuit and the output DN and DW of the comparison circuit is tentatively stored, to output the width comparison data every one character

High speed to low speed data buffering means

Abstract: A system is provided in which a memory is divided into two parts, so that a substantially continuous printing operation can be carried out by reading information to be printed from one part of the memory, with printing being interrupted for brief periods of time to permit writing of information in the other part of the memory. The writing into the memory is done on an alternate line basis, with the omitted lines being filled during a subsequent write operation so as to convert the interlace input to a standard format. At an appropriate time, the two parts of the memory are switched so that the read-out for the printing is carried out from the part into which information has just been written, and the writing takes place in the part of the memory which has been cleared during the preceding read operation.