Showing papers on "Redundancy (engineering) published in 1985"

Code Combining--A Maximum-Likelihood Decoding Approach for Combining an Arbitrary Number of Noisy Packets

Abstract: It is well known that if the data rate is chosen below the available channel capacity, error-free communication is possible. Furthermore, numerous practical error-correction coding techniques exist which can be chosen to meet the user's reliability constraints. However, a basic problem in designing a reliable digital communication system is still the choice of the actual code rate. While the popular rate-1/2 code rate is a reasonable, but not optimum, choice for additive Gaussian noise channels, its selection is far from optimum for channels where a high percentage of the transmitted bits are destroyed by interference. Code combining represents a technique of matching the code rate to the prevailing channel conditions. Information is transmitted in packet formats which are encoded with a relatively high-rate code, e.g., rate 1/2, which can be repeated to Obtain reliable communications when the redundancy in a rate-1/2 code is not sufficient to overcome the channel interference. The receiver combines noisy packets (code combining) to obtain a packet with a code rate which is low enough such that reliable communication is possible even for channels with extremely high error rates. By combining the minimum number of packets needed to overcome the channel conditions, the receiver optimizes the code rate and minimizes the delay required to decode a given packet. Thus, the receiver adapts to the actual jammer-to-signal (J/S) ratio which is critical when the level of interference J is not known a priori.

Redundancy resolution of manipulators through torque optimization

Abstract: Methods for resolving kinematic redundancies of manipulators by the effect on joint torque are examined. When the generalized inverse is formulated in terms of accelerations and incorporated into the dynamics, the effect of redundancy resolution on joint torque can be directly reflected. One method chooses the joint acceleration null-space vector to minimize joint torque in a least squares sense; when the least squares is weighted by allowable torque range, the joint torques tend to be kept within their limits. Contrasting methods employing only the pseudoinverse with and without weighting by the inertia matrix are presented. The results show an unexpected stability problem during long trajectories for the null-space methods and for the inertia-weighted pseudoinverse method, but more seldom for the unweighted pseudoinverse method. Evidently, a whiplash action develops over time that thrusts the endpoint off the intended path, and extremely high torques are required to overcome these natural movement dynamics.

A Fault-Driven, Comprehensive Redundancy Algorithm

Abstract: This article describes a fault-driven algorithm that generates all possible repair solutions for a given bit failure pattern in a redundant RAM. Benefits of this approach include the ability to select repair solutions based on userdefined preferences (for example, fewest total elements invoked or fewest rows invoked). Perhaps the greatest advantage of this algorithm is its ability to generate solutions for any theoretically repairable die that would be deemed unrepairable by existing algorithms.

Adaptive cross-parity (AXP) code for a high-density magnetic tape subsystem

Abstract: This paper describes an error-correction system, called adaptive cross-parity (AXP) code, for the IBM 3480, a new high-density 18-track tape storage subsystem. Redundancy is applied to two interleaved sets of nine tracks in the same proportion as that in the previous IBM 3420 tape machines. The coding structure, however, is simpler, for it avoids the complex computations of Galois fields. The coding structure is based on a concept of interacting vertical and cross-parity checks, where the cross-parity checks span both sets of tracks and are used in either set in an adaptive manner. As a result, the overall error-correcting capability is substantially improved without increasing the redundancy. Decoding, in which simple parity equations are processed, is designed to progress iteratively. By means of adaptive use of redundancy, the new method corrects up to three known erroneous tracks in any one set of nine tracks and up to four known erroneous tracks in the two sets together. The code also identifies the first unknown erroneous track in each of the two sets, and subsequently identifies the second unknown erroneous track in one of the two sets while providing correction for all these tracks. The result is generalized for a system with any number of tracks divided into a multiple number of unequal sets.

An integrated approach to the layout and design of water distribution networks

Abstract: A model for the least cost layout and design of looped water distribution networks has been developed. The model consists of two linked linear programming formulations. One linear program determines the least cost layout of a looped distribution network given an initial pressure distribution. The other model determines the least cost component design given an initial flow pattern or pipe layout. The linkage between the two linear programs is provided by the use of output from one linear program as input to the other. Since the constraints in the layout model may provide looping without ensuring true redundancy in the system, a layout review is necessary after solutions of the layout model. If true redundancy is not present a set of ‘optional’ constraints can be applied and the layout model solved again. The procedure is demonstrated by application to a sample network.

Dynamically Restructurable Fault-Tolerant Processor Network Architectures

Abstract: A class of novel fault-tolerant multiprocessor networks is proposed. These networks are restructurable in that they can assume different logical configurations to suit different problem environments. More importantly, this restructuriing capability is not altered even after the occurrence of faults. These networks are novel in that they uniquely combine certain desirable features, including self-routing of messages, dynamic reconfigurability, fault-tolerance, the ability to incorporate incremental extension, as well as the capacity to be partitioned with fault-tolerance. What is important about these fault-tolerant features is that they are built-in as an integral part of the design, and not as done traditionally, by means of redundancy.

Sensor failure detection for jet engines using analytical redundancy

Abstract: Analytical redundant sensor failure detection, isolation and accommodation techniques for gas turbine engines are surveyed. Both the theoretical technology base and demonstrated concepts are discussed. Also included is a discussion of current technology needs and ongoing Government sponsored programs to meet those needs.

Programmable redundancy circuit

Abstract: A memory redundancy circuit is described incorporating a sequential row or column counter associated with a plurality of programmable row or column decoders. The sequential row counter includes a sequence circuit for each programmable row decoder.The sequence circuit and programmable row decoder incorporate fixed and variable threshold transistors such as metal nitride oxide semiconductor (MNOS) transistors. The threshold of the variable threshold transistors are switched in response to address signals and control signals to permit redundancy. A disable circuit is also described to permit removal of the redundancy circuits to permit retest of the other circuits.

A Production System for Use of Global Optimization Knowledge

Abstract: A method employing ideas from applied artificial intelligence is proposed for use in design optimization. Knowledge of global information is incorporated in several rule types concerning constraint activity, redundancy, and dominance. The rules are organized in a production system that makes deductions about possible (globally) active sets. Two design examples demonstrate the strategy. Similar ideas may be used in other areas of the optimization process, particularly in design applications.

Bad Data Suppression in Power System State Estimation with a Variable Quadratic-Constant Criterion

Abstract: This paper reports numerical results on tests of a new bad data suppression strategy for power system state estimation. A transformation-decoupled state estimator [1] is used in conjunction with a variable quadratic-constant criterion whose break even point is designed to track the upper bound of normalized residues of good measurements. Numerical simulations with a 6-bus test system and the IEEE 30-bus system show that the new bad data suppression strategy, is very effective for different systems under many uncertainties in the sizes and numbers of bad data with a moderate measurement redundancy.

Generating storage reference instructions in an optimizing compiler

Abstract: A method for improving the quality of code generated by a compiler in terms of execution time, object code space, or both. The method is applicable to computers that have a redundancy of instructions, in that the same operation exists in forms that operate between registers, between main storage locations, and between registers and main storage. The method selects the best form of each such instruction to use, for the context in which the instruction lies.

Overspeed system redundancy monitor

Abstract: A redundancy monitor is presented which makes operational checks on the electronic overspeed control system used on aircraft turbine engines. The monitor is a small and lightweight device that can be permanently installed on the engine. Its function is to monitor both the speed pickups that count the revolutions per minute that the turbine shaft is turning and at the same time maintain a check on the performance of the circuitry which processes the data. The monitor includes a latching type BITE indicator which signifies redundant status of the speed pickups and a lamp which lights to indicate any failure in the output circuitry of the overspeed sensor system. A momentary-on type switch activates self test circuitry within the redundancy monitor.

Point defect yield model for wafer scale integration

Abstract: Yield projections are a primary consideration in wafer scale integration. The author develops a point defect yield model for a two-way redundancy scheme appropriate for random logic. The model assumes that the fault-causing defects are randomly distributed locally but that the defect density can vary across a wafer as well as from one wafer to another. Examples are given to illustrate the strong dependence of the results on clustering of defects and on the redundancy partitioning. The importance of the distinction between on-wafer and wafer-to-wafer variations in defect density is demonstrated. Complications associated with the occurrence of small numbers of highly correlated defects are discussed.

Bipolar-transistor type semiconductor memory device having a redundancy configuration

Abstract: A bipolar-transistor type semiconductor memory device includes a memory cell array (1), a redundancy memory cell array (10), a redundancy driving circuit (11), and a redundancy address decision circuit (12,13). The redundancy driving circuit includes an emitter-coupled logic gate (Q20,Q21,R8,IS14) which compares the voltage level of an input signal with a reference voltage level to produce an enabling signal for the redundancy memory cell array. When the redundancy address decision circuit judges that the input address coincides with the address of a defective circuit portion of the memory device, the redundancy driving circuit operates to enable the redundancy memory cell array instead of the normal memory cell array.

Functionally redundant logic network architectures with logic selection means

Abstract: A programmable gate structure (20) having functionally redundant architeture for enhanced production yields and reliability comprises a plurality of two-input nodes (10) at least some of which may be programmed by control states (24, 26 and 28) for changing the logical function of the gate structure. Redundancy is provided by gate structure implementations in which the number of possible control states exceed the number of logic functions expected of the gate structure. Redundancy increases the probability of gate structure operation despite logic faults and renders the gate structure suitable for reprogramming in response to detected faults to achieve a desired gate function. A number of embodiments are disclosed including selected architectural simplifications wherein certain nodes in a network are logically fixed to reduce the number of control lines. Illustrative computer programs for generating the proper control line signals for a selected gate function in such embodiments are disclosed.

Rechnersystem mit zwei prozessoren

Abstract: A computer system comprising two processors (P1, P2) to control the parameters of an internal combustion engine, in particular to adjust the digital controller of a Diesel injection pump. Both processors (P1, P2) share in normal operation the computing duties, and in the case of a breakdown each of the processors (P1; P2) can, acting as a stand-by computer, provide an emergency operating mode. Through greater redundancy and shared duties in normal operation it is possible to considerably increase safety and speed of operation.

Evaluation of the File Redundancy in Distributed Database Systems

Abstract: This paper treats the file redundancy issue in distributed database systems, asking what is the optimal number of file copies, given the ratio r of the frequency of update requests to the frequency of all file access requests (i.e., queries and updates). Formulations of this type of problem, including optimal file allocation, have been attempted by a number of authors, and some algorithms have been proposed. Although such algorithms can be used to solve particular problems, it seems difficult to draw general conclusions applicable to a wide variety of practical distributed database systems. To probe into this hard to formulate but interesting problem, our paper constructs simplified network models of distributed database systems, and computes the optimal number of file copies, as well as their locations, to minimize the communication cost. For several network types, we plot the optimal number of file copies as a function of the ratio r.

64Kb ECL RAM with redundancy

Abstract: A 64Kw x l b bipolar ECL RAM with two-array redundancy will be described. This device, using a PNP load cell, was fabricated in IOP-I1 (second generation of Isolation by Oxide and Polysilicon) and 1 . 2 ~ lithography. A redundant circuit configuration was applied to the RAM, without deterioration of the high speed characteristics of ECL. Decoder circuits with jun,ction shorting PROM, can be reliably programmed, and enhance yield, as much as the present.16Kb ECL RAM. Two spare arrays were prepared for row and column; Figure 1. The speed of the spare arrays for decoding has been found to be equivalent to that provided by ordinary decoders, because the only dc high or low voltages to the compare gates are generated by the PROM circuit. But this additional redundant circuit increases the number of peripheral gates and the power dissipation. To overcome this problem, the following circuits were introduced: ( I ) a low power second stage column decoder (most of the unselected driver gates do not require current flow for low output levels); (2) a Darlington word driver with pull down resistance (the high current gain of the Darlington transistor decreases the power of word driver gates); Figure 2. The PNP load cell, includes a P-type deep emitter and collector for fast write switching: additionally, the cell affords control of the beta of the read/write transistor for a decrease of the parasitic sink current’. These diffusions have been merged into a single P-type step (Figure 3) which shortens masking steps and reduces cell area. Fine line 1.2p lithography has also been employed. The minimum emitter size is 1 .21 x 2.41 and the minimum linewidth plus spacing of the first and second metal layers are 4 . 0 ~ and 5 . 0 ~ respectively. Isolation width is 2.4F Cell area is 52412, while die size is 55.4mm2. A typical address access time of lOns has been obtained. Figure 4 shows switching waveforms of the address input and data output. A microphotograph of the chip is shown in Figure 5. Characteristic features of this RAM and typical transistor parameters are summarized on Tables 1 and 2. By applying 1.01 lithography, sub lOns performance is expected.

Semiconductor memory device having a redundancy circuit

Abstract: A semiconductor memory device including a random-access memory (RAM) having at least one redundancy column for replacing a defective column, a serial output circuit (SR,...SRn) for reading out in parallel and outputting serially data stored in the random access memory, and a redundancy circuit (RA, 4,5,6,7,DC1,RSA) for replacing data of the defective column with data of the redundancy column.

Redundancy system and switching network

Abstract: A redundancy switching system which provides four reserve devices is disclosed which is suitable for use with from eight to twelve channels. The switches in the input switching network of this redundancy system are connected in first and second sections. Each section includes a ring of switches and two switches connected as appendages to the ring. Only as many switches are needed to control the input connection to the redundant devices as there are redundant devices. A similar number of switches are needed to control the output connection of the active devices.

Implicit motion compensated noise reduction of motion video scenes

Abstract: Signals derived from video systems which generate motion picture scenes possess a great deal of temporal redundancy. The temporal correlation of adjacent frames is often completely determined by the displacement field, which over the course of time traces out the motion trajectories of moving objects within the scene. It is possible to exploit the available redundancy in these signals for the purpose of noise reduction by compensating for the presence of motion. We present an adaptive filtering technique which implicitly compensates for motion within a scene by performing 1-D signal estimation along a set of hypothesized motion directions. This technique adapts the estimator parameters to the local image characteristics along a set of specified directions in the 3-D signal space. Experiments with real life scenes have shown that this method achieves substantial noise reduction in many cases, while preserving the edge contrast of the desired signal.

Time- and Frequency-Domain Analysis of Linear Switched-Capacitor Networks Using State Charge Variables

Abstract: We formulate the state equations for tme- and frequency-domain aalysis of switched-capacitor networks (SCN's) using charges associated with topologically identifiable structures in a network as network variables. The method effectively combines variable elimination to reduce matrix sizes with redundancy elimination to reduce memory requirements for many-phases SCN's. The frequency-domain analysis equations are formulated in such a way that computation can be done in a simple iterative manner akin to time-domain analysis but without using discrete Fourier transform. Two speed-up algorithms based on the proposed formulation for input and output sampling are presented.

A technique for organizing large moment calculations for use with iterative solution methods

Abstract: Through a specific choice of evenly spaced basis and testing functions, one can construct a moment matrix formulation wherein significant redundancy is embodied in the matrix. A scheme that exploits this redundancy to effect substantial computer storage reduction in an iterative field solution, such as the conjugate-gradient method is described. The expense incurred is a modest increase in computation time. The redundancy results from translational similarity features of specific classes of geometries and leads to matrix equations that may be interpreted as discrete convolutions. For illustration, the analysis here is carried out on a planar scatterer, but the strategy can be applied to spherical or cylindrical scatterers.

Reliability Evaluation and Optimization of Redundant Dynamic Systems

Abstract: This paper analyzes the reliability of a simple dynamic system with redundant element and demonstrates an optimization technique for system reliability. A computer program was implemented to calculate the true reliability and the near optimal redundancy allocation for a dynamic subsystem. The solutions for the examples were always truly Optimum which is illustrated by an example.

Feature determination and inexact matching of images of industrial components

Abstract: Techniques for the segmentation and recognition of images of overlapping industrial components in visually cluttered environments are described. Image segmentation is based on the Hough transformation of preprocessed edge data, employed as a predictive mechanism for line fitting, merging and redundancy checking, coupled with feedback verification. In the recognition phase, the extracted features are matched inexactly against a database of known models. Hypotheses are based on local feature matches and verified, first, by comparison of a translated and rotated prototype with the feature data, and, secondly, by re-examination of the original gradient data. Examples of experiments performed on single and multiple-component images are presented, demonstrating the robustness of the method.

Optical adaptive linear predictors.

Abstract: Adaptive linear predictors have found important application in channel equalization, source redundancy removal, speech encoding and analysis, interference and noise rejection, signal classification, adaptive control, and adaptive antenna systems. In an effort to provide adaptive linear predictors of wide bandwidth, several optical implementations have been proposed. This paper reviews and analyzes the existing optical architectures, putting them in a common framework. Four new common-path architectures are proposed and compared with the others.