Showing papers on "Routing (electronic design automation) published in 1972"
Patent•
25 Sep 1972
TL;DR: In this paper, a pallet consisting of a plurality of printed circuit boards is interconnected by snapaway perforated edges at the adjacent side of the boards, so that the pallet consists of plural boards is processible as a whole.
Abstract: In a process for producing calculator printed circuit boards, a pallet consisting of a plurality of printed circuit boards are interconnected by snapaway perforated edges at the adjacent side of the boards, so that the pallet consisting of plural boards is processible as a whole. Electrical elements or components have their terminals received through openings in the printed circuit board, which insertion is by machine utilizing a pantographic locating principle. Components are also assembled on the board by hand insertion. After inserting selected electrical components at the desired locations, and masking other locations, the electrical connections are then treated by fountain soldering to form electrical connections between the leads and the printed circuit. The soldering occurs to the pallet as a whole. The individual boards are then snapped apart and the board has enough dimensional stability so that it is rigidly clamped on a fixture and passed over a routing blade at a predetermined slight clearance therefrom so that all of the excess lead sections are trimmed from the subsurface of the printed circuit substrate. Further electrical devices can then be added and soldered in place and the printing circuit board together with its electrical components can then be positioned within a container for a computer application. The described process incorporates minimal handling and incorporates high speed machine assembly techniques wherein multiple operations occur simultaneously or repetitively at high speed.
55 citations
TL;DR: Experimental evidence is presented to show that the performance of a router, when measured in terms of the total of the minimum (or ideal) lengths of the connections successfully completed, is, in fact, independent of the order in which connections are attempted.
Abstract: Most wire-routing programs utilize a maze-running technique to route one connection at a time. Once routed, a wire cannot be moved even if it is subsequently discovered to interfere with the successful completion of other connections. The order in which the desired connections are presented to the routing algorithm has therefore been thought to be of critical importance. Experimental evidence is presented, however, to show that the performance of a router, when measured in terms of the total of the minimum (or ideal) lengths of the connections successfully completed, is, in fact, independent of the order in which connections are attempted.
47 citations
TL;DR: The problem of determining minimum-time ship routes is expressed as a discrete decision process in stochastic conditions, and is solved by dynamic programming, and example trajectories are presented.
Abstract: In this paper the problem of determining minimum-time ship routes is expressed as a discrete decision process in stochastic conditions, and is solved by dynamic programming. Some models of such processes are considered. Their applicability depends on the amount of available meteorological information. The salient features of the computer programs, operating experimentally aboard a motorship in normal service, are illustrated and example trajectories are presented.
45 citations
26 Jun 1972
TL;DR: The method described in this paper assigns a vector to each available chip pin and to each set of connections which are to be connected to a single pin on the chip following a heuristic optimization procedure that gave a significant improvement in the number of wires routed on a large sample of typical boards.
Abstract: The success of a router in automated printed circuit board design depends strongly on board organization prior to routing. One of the steps in board organization is the assignment of connections to pins, which can be made with considerable freedom since most chips have permutable circuits, gates, or gate input pins. Intelligently made pin assignment can reduce the two principal causes of router failure: (1) the crossing of connection paths and (2) the filling of available channels. The method described in this paper assigns a vector to each available chip pin and to each set of connections which are to be connected to a single pin on the chip. These vectors are used to assign the connections to the pins following a heuristic optimization procedure. This procedure was implemented as a FORTRAN program and gave a significant improvement in the number of wires routed on a large sample of typical boards. It is now incorporated into the UNIVAC automated P.C. board design program.
40 citations
26 Jun 1972
TL;DR: The implementation of an automatic router for the custom design of MOS integrated circuits is presented and, because of its very low cost, can allow manual intervention to achieve more efficient layouts.
Abstract: This paper presents the implementation of an automatic router for the custom design of MOS integrated circuits. Standard cells are utilized for the logical functions and are interconnected by the router according to the specific design being produced. The design program operates at a very low cost and yields results comparable to manual routing. An expansion technique is used which will give 100 percent completion of interconnection. The router will handle any cell size and will route according to any predetermined design rules. An accuracy of one-hundredth of a mil can be maintained on chips over 300 mils on a side. The router may be used to build designs automatically or, because of its very low cost, can allow manual intervention to achieve more efficient layouts.
35 citations
TL;DR: The wire routing problem in the layout of integrated circuits is formulated as Steiner's problem in graphs and a suboptimal algorithm is described for the problem based on the branch-and-bound method.
Abstract: The wire routing problem in the layout of integrated circuits is formulated as Steiner's problem in graphs. A suboptimal algorithm is described for the problem. The algorithm is based on the branch-and-bound method. The result of the algorithm applied to several examples is also described.
26 citations
IBM1
TL;DR: Criteria recently developed for optimum capacity assignment in message-switching networks are applied to a network model which now contains nodal processors as well as interconnecting links, and various performance and cost-performance curves are presented.
Abstract: Criteria recently developed by the authors for optimum capacity assignment in message-switching networks are applied to a network model which now contains nodal processors as well as interconnecting links. Linear and stepped cost functions are examined and various performance and cost-performance curves are presented. An efficient design procedure is described for the tedious case of stepped cost functions. For general continuous cost functions and the minimax design the distribution functions of all point-to-point delays can be easily calculated.
16 citations
26 Jun 1972
TL;DR: A routing procedure is given which is different from Lee type algorithms in that it considers a large group of interconnections simultaneously.
Abstract: A routing procedure is given which is different from Lee type algorithms in that it considers a large group of interconnections simultaneously. A finite number of path classes are established and an algorithm is given for finding the maximum number of non-intersecting interconnections which can be routed if the paths are restricted to these classes. Procedures are given for drawing all interconnections which have been assigned to some path class.
9 citations
TL;DR: The partitioning of the abstract graph representing an electronic circuit has been applied to the placement of components on a printed wiring board and results obtained from a computer program exhibit a marked degree of similarity to placements produced by a skilled draughtsman for a very low processing cost.
Abstract: The partitioning of the abstract graph representing an electronic circuit has been applied to the placement of components on a printed wiring board. Results obtained from a computer program exhibit a marked degree of similarity to placements produced by a skilled draughtsman, for a very low processing cost.
7 citations
TL;DR: A simpler and more compact formulation of this problem results in an Integer Program of considerably reduced size, that can more naturally serve as a basis for finding suitable branch-and-bound methods for its solution as mentioned in this paper.
Abstract: This note is a comment on the paper by LEVIN and discusses the problem of fleetsize minimization for transportation systems. A simpler and more compact formulation of this problem results in an Integer Program of considerably reduced size, that can more naturally serve as a basis for finding suitable branch-and-bound methods for its solution.
01 Jan 1972
TL;DR: The detailed engineering decisions that can be made by computer in the design of practical large-scale networks are illustrated by example for cable television systems to indicate the richness and difficulty of the problem of applying computers to network design.
Abstract: The application of computer techniques to difficult large-scale network problems is discussed. The physical characteristics of two types of systems are described--computer-communication networks and cable television distribution systems. Two fundamental algorithms are presented, and applications to routing, reliability, and design of computer networks are given. The detailed engineering decisions that can be made by computer in the design of practical large-scale networks are illustrated by example for cable television systems. These examples are chosen to indicate the richness and difficulty of the problem of applying computers to network design.
Journal Article•
TL;DR: In this article, the authors present a one-pass constant capacity restraint (Crestrest) scheme, which provides a flexible and economical tool for planning and assigning traffic assignment with stable speed-flow relations.
Abstract: MULTIPLE ROUTING, AS PRESENTED HERE, ADDS THROUGH ITS STOCHASTIC PRINCIPLE A LONG-SOUGHT ELEMENT OF REALISM TO THE TRAFFIC ASSIGNMENT PROCESS. THIS PRINCIPLE ELIMINATES THE PROBLEM ASSOCIATED WITH THE MINIMUM PATH PROCEDURE, WHICH LEADS TO EXTREMELY UNBALANCED FLOWS WHERE MORE THAN ONE ACCEPTABLE ROUTE EXISTS BETWEEN PAIRS OF NODES. WITH THE MULTIPLE ROUTING PRINCIPLE AS ITS BASIC FRAMEWORK, A ONE-PASS INCREMENTAL CAPACITY RESTRAINT PROCEDURE IS PRESENTED, WHICH PROVIDES A FLEXIBLE AND ECONOMICAL TOOL FOR PRODUCING TRAFFIC ASSIGNMENTS WITH STABLE SPEED-FLOW RELATIONSHIPS. RESULTS OBTAINED WITH THIS PROCEDURE INDICATE A LEVEL OF ASSIGNMENT ACCURACY WHICH IS EQUIVALENT OR SUPERIOR TO THAT OBTAINED WITH FOUR ITERATIONS OF THE FREQUENTLY USED AVERAGING PROCEDURE. /AUTHOR/
26 Jun 1972
TL;DR: The procedure presented in this paper may be applied to take fuller advantage of the computer's capabilities to accomplish the more tedious tasks in computer design.
Abstract: Design automation processors are best known for their ability to competently accomplish the more tedious tasks in computer design. Almost invariably they are restricted to tasks which occur after the logic design is completed (diagnosis, partitioning, assignment, routing, etc.). The procedure presented in this paper may be applied to take fuller advantage of the computer's capabilities.
26 Jun 1972
TL;DR: In the sequence of events normally associated with the design cycle for a digital system, the two operations where simulation has the greatest impact are at opposite ends of the cycle, the Design Verification step and the Functional Test Generation step.
Abstract: In the sequence of events normally associated with the design cycle for a digital system, the two operations where simulation has the greatest impact are at opposite ends of the cycle. These are the Design Verification step and the Functional Test Generation step in Figure 1.Between Design Verification and Test Generation, the implementation, partitioning, packaging, placement, and routing operations are performed. These operations lead to a complete design, and all work from a common data base. Each step in the cycle augments the data base as the design progresses from concept to hardware.
TL;DR: A Monte Carlo simulation program that enables the evaluation of different routing policies in a communication network is described and a significant improvement in the G/S is obtained for the policy that aimed at distributing the flow through the network in the most homogenous way possible.
Abstract: A Monte Carlo simulation program that enables the evaluation of different routing policies in a communication network is described This simulation is intended to deal with nonoriented (telephone) networks and the grade of service (G/S) is taken as the performance measure However, it can easily be adapted to deal with oriented or mixed networks The program assigns to each branch of the analyzed network a price function For each call, the route of minimal cost, among all available under the present load conditions in the network, is then chosen The program was used for comparing routing policies, as initiated by different price functions The comparisons were made on several test networks and for different traffic loads The results obtained showed a significant improvement in the G/S for the policy that aimed at distributing the flow through the network in the most homogenous way possible This homogenous flow distribution was obtained by using the above minimal-cost policy and a price function, assigned to each channel, that monotonically increases with the traffic load of the branch to which the particular channel belongs The influence of the topological configuration of the network on the G/S, under equal external demands, was also investigated and the results are given The way in which the results are printed out enables the simulation program to serve also as a practical and useful tool in the design (or the redesign) of a communication net
Patent•
17 May 1972
TL;DR: In this paper, a precision cutoff and routing device including a support frame having locating and positioning elements thereon, with a cutting unit mounted for movement thereon which cutting unit includes material clamping members, a traversing cutting element and a plurality of routing devices which routing devices are arranged for controlled movement within a predetermined path for precisely routing a connector receiving recess in the bottom of the material being cut which recess may be formed on either side of the path of the traversing cut element.
Abstract: A precision cutoff and routing device including a support frame having locating and positioning elements thereon, with a cutting unit mounted for movement thereon which cutting unit includes material clamping members, a traversing cutting element and a plurality of routing devices which routing devices are arranged for controlled movement within a predetermined path for precisely routing a connector receiving recess in the bottom of the material being cut which recess may be formed on either side of the path of the traversing cutting element. Control means are provided to prevent movement of the routing devices through the path of the cutting element while the cutting element is moving.
TL;DR: Results indicate that the out-of-Kilter algorithm is more EFFICIENT in the SOLUTION of the ORIGINAL PROBLEM when there is a MODERATE NUMBER of COMMODities and a COMPUTER of LIMITED STORAGE CAPACITY.
Abstract: IN THIS JOURNAL IN 1967, SZWARE PRESENTED AN ALGORITHM FOR THE OPTIMAL ROUTING OF A COMMON VEHICLE FLEET BETWEEN M SOURCES AND N SINKS WITH P DIFFERENT TYPES OF COMMODITIES. THE MAIN PREMISE OF THE FORMULATION IS THAT A TRUCK MAY CARRY ONLY ONE COMMODITY AT A TIME AND MUST DELIVER THE ENTIRE LOAD TO ONE DEMAND AREA. THIS ELIMINATES THE PROBLEM OF ROUTING VEHICLES BETWEEN SOURCES OR BETWEEN SINKS AND LIMITS THE PROBLEM TO THE ROUTING OF LOADED TRUCKS BETWEEN SOURCES AND SINKS AND EMPTY TRUCKS MAKING THE RETURN TRIP. SZWARE CONSIDERED ONLY THE TRANSPORTATION ASPECT OF THE PROBLEM (I.E., NO INTERMEDIATE POINTS) AND PRESENTED A VERY EFFICIENT ALGORITHM FOR SOLUTION OF THE CASE HE DESCRIBED. IF THE TOTAL SUPPLY IS GREATER THAN THE TOTAL DEMAND, SZWARE SHOWS THAT THE PROBLEM IS EQUIVALENT TO A (MP + N) BY (NP + M) HITCHCOCK TRANSPORTATION PROBLEM. DIGITAL COMPUTER CODES FOR THIS ALGORITHM REQUIRE RAPID ACCESS STORAGE FOR A MATRIX OF SIZE (MP + N) BY (NP + M); THERFORE, COMPUTER STORAGE REQUIRED GROWS PROPORTIONALLY TO P SQUARED. THIS PAPER OFFERS AN EXTENSION OF HIS WORK TO A MORE GENERAL FORM: A TRANSSHIPMENT NETWORK WITH CAPACITY CONSTRAINTS ON ALL ARCS AND FACILITIES. THE PROBLEM IS SHOWN TO BE SOLVABLE DIRECTLY BY FULKERSON'S OUT-OF-KILTER ALGORITHM. DIGITAL COMPUTER CODES FOR THIS FORMULATION REQUIRE RAPID ACCESS STORAGE PROPORTIONAL TO P INSTEAD OF P SQUARED. COMPUTATIONAL RESULTS INDICATE THAT, IN ADDITION TO HANDLING THE EXTENSIONS, THE OUT-OF-KILTER ALGORITHM IS MORE EFFICIENT IN THE SOLUTION OF THE ORIGINAL PROBLEM WHEN THERE IS A MODERATE NUMBER OF COMMODITIES AND A COMPUTER OF LIMITED STORAGE CAPACITY. /AUTHOR/
TL;DR: A NIM standard module is described which provides the binary timing words for memory routing necessary for multispectral scaling and a circuit is included which insures the tagging of the ADC address with the correct timing word even for time bases which are short compared to the ADC conversion time.
01 Jan 1972
TL;DR: In this article, a serial partition of the problem of circuit design is presented. But the layout is not considered. And the layout functions are done concurrently, which provides for greater feedback between the different functions, and therefore greater efficiency, as more relevant information is available to each function.
Abstract: : The report describes a new apporach to the automatic design of printed circuit boards. In the past, the problem has been partitioned by design functions. The generally recognized functions are pin assignment, component placement, and wire routing or layout. This is essentially a serial partition of the problem. Instead of producing the layout wire by wire, as is currently the rule, the layout is produced by traversing the board in a raster scan fashion, routing all relevant wires in parallel. This allows all design functions to be accomplished simultaneously. The fact that the layout functions are done concurrently provides for greater feedback between the different functions, and therefore greater efficiency, as more relevant information is available to each function. (Modified author abstract)
01 Dec 1972
26 Jun 1972
TL;DR: The evolving Automated Design System has the following functional capabilities: logic equation handling, logic simulation, automated logic diagrams, automated board layout and routing, and artwork generation.
Abstract: The increased complexity of computing systems, combined with the economic necessity of rapid system development, has resulted in the allocation of considerable computerized aids to the development process. Such automated design aids have been used by the major computer manufacturers to facilitate design, documentation, manufacturing, and testing of computer systems. UNIVAC has used computer aided design since 1958 with many processes and aids now essential in development efforts. The evolving Automated Design System is illustrated. This system has the following functional capabilities: logic equation handling, logic simulation, automated logic diagrams, automated board layout and routing, and artwork generation. Section 2 of this paper contains a description of the Automated Board Layout and Routing Subsystem, including a description of the algorithm used for routing. The remaining subsystem is described in the following paragraphs.
01 Aug 1972
TL;DR: An interactive system for the design of printed circuit boards that uses an interactive graphics terminal for solving the placement and routing problems and provides significant savings in both design time and processing costs over batch processing and manual methods.
Abstract: This paper describes an interactive system for the design of printed circuit boards. The system uses an interactive graphics terminal for solving the placement and routing problems. It can be used for designing two-layer boards with integrated circuit modules and discrete components. A substantial portion of the wire-routing is performed automatically and the remaining wires are routed manually in a single interactive session. The system provides significant savings in both design time and processing costs over batch processing and manual methods.
TL;DR: Routing systems were developed for seven different cases, each designed to evaluate a specific policy question, and the procedure was illustrated utilizing a problem in wholesale food distribution.
Abstract: The "lockset" routing technique can be used to answer policy questions concerning assembly or distribution systems as well as to design routes for assembly or distribution systems. The procedure was illustrated utilizing a problem in wholesale food distribution. Routing systems were developed for seven different cases, each designed to evaluate a specific policy question.