Showing papers on "Sense amplifier published in 1983"

A memory system for storing analog information

Abstract: The non-volatile semiconductor memory elements hav­ ing an MlS structure show a hysteresis curve in the gate voltage - the threshold voltage characteristic. The con­ tinuously changing region of the hysteresis curve is used to operate the memory elements as analog memories. The input analog signal is applied to the gate electrode of a selected memory element after it is converted to have a voltage within the continuously changing region, to change the threshold voltage of the selected memory element. The changed threshold voltage is read out in read-out operation.

Bus oriented LIFO/FIFO memory

Abstract: There is disclosed a modular memory cell structure including a data latch, an occupancy bit latch and control logic. Each memory cell has access to the occupancy bit status of adjacent cells and to the input, output, control, and status busses. The occupancy status provides positional address information enabling each cell to determine if data in its data latch is the first, intermediate, or last element of a data queue. When a group of memory cells and an initialization circuit are interconnected, a modular integrated circuit design results which can function as either a first in-first out (FIFO) or a last in-first out (LIFO) memory.

Semiconductor memory with an improved dummy cell arrangement and with a built-in error correcting code circuit

Abstract: In a read only semiconductor memory, signal lines such as data lines are subjected to an undesired parasitic capacitance which restricts the signal changing rate along the lines. The parasitic capacitance which is driven by a memory cell will become increasingly higher as the memory capacity is increased. According to the present invention, a differential sense amplifier is used to amplify the data signals which are read out of the memory cell. At the same time, a dummy cell is used to generate a reference potential which is to be referred to by the differential sense amplifier. In particular, a dummy cell arrangement is provided wherein each dummy cell includes at least two series-connected semiconductor elements to provide a predetermined dummy cell conductance to establish a reference value. Another aspect of the invention lies in the use of column switches between a common data line and data lines of the memory arrays for coupling only one data line at a time through the column switch to the sense amplifier. In addition, a built-in error-correcting-code circuit is provided which operates in conjunction with a selecting circuit so that memory cells delivering a predetermined set of data are spaced apart from one another by at least predetermined distances to reduce the likelihood of errors from immediately adjacent memory cells.

Semiconductor memory device having a voltage push-up circuit

Abstract: A semiconductor memory device includes charge storage type memory cells, word lines and a bit line connected to the memory cells, a sense amplifier for detecting the memory data on the bit line, and a voltage push-up circuit for setting up a potential on the bit line. The voltage push-up circuit at first sets the potential on the bit line at a power supply voltage level after the memory data having a high logic level is detected by the sense amplifier, and then pushes up the potential on the bit line to a higher potential level than the power supply voltage.

Communicating random access memory

Abstract: A communicating random access shared memory configuration for a multiprocessor system is connected to the processors for transferring data between the processors. The random access memory configuration includes a plurality of interconnected random access memory chips, each of these memory chips including first and second separate memory bit arrays having N word storage locations of M bit length with M bit buffer connected in between the first and second bit arrays on each memory chip, and first and second input/output ports connected to first and second bit arrays on each chip for entering and removing data externally to and from the chip. A controller is located on each chip and connected to the first and second memory arrays and the M bit buffer for transferring data between the first and second memory arrays and into and out of the first and second input/output ports.

Semiconductor memory cell

Abstract: PURPOSE: To attain high integration with a memory which can work with binary voltage without deterioration of read-out signals obtained by miniaturizing a memory cell, by sharing both writing and reading digit lines and providing functions to the memory cell for amplification of its stored signals. CONSTITUTION: When the 2nd FET 2 is turned on with the binary voltage via a writing word line 6, the potential of a charge storing node is decided in response to the data on a digit line 5. Thus the binary data is written and then amplified via a capacity when the binary voltage is supplied to a reading word line 7. Then the 1st FET 1 having threshold voltage is turned on or off in response to the binary data. Then the reference potential passed through the FET 1 or an OFF potential is read out via a sense amplifier connected to the line 5. Thus the line 5 is used in common for both writing and reading operations. This attains high integration with a memory. COPYRIGHT: (C)1987,JPO&Japio

CMOS memory cell having an electrically floating storage gate

Abstract: An electrically programmable memory cell contains a source-drain series arrangement of a field-effect select transistor arrangement and a complementary pair of memory transistors arranged between a first bit line and a second bit line. The pair of memory transistors comprises a common electrically floating storage gate and a common control gate which is connected to one programming line. Each of the electrodes of the select transistors is connected to the row selecting line associated therewith. The drain regions which are connected to one another, are lead to a read line. The memory cell according to the invention permits reading without requiring any significant DC power, and programming by using the complete programming voltage as available.

Submicron VLSI memory circuits

Abstract: cell, alpha-induced soft-errors, are a serious problem. A solution is an on-chip ECC technique using bidirectional parity checking. A logic diagram of a RAM with on-chip ECC circuits is shown in Figure 1. In addition to (k x m) fundamental memory cells, (k tm) parity cells are connected with each word line. All of the cells along the same word line compose an ECC data set for bidirectional parity checking. Each element of this data in the fundamental memory cells belong t o two imaginary groups; V and H. In the reading cycle, two types of parity checking occur using m-bit V-group, k-bit H-group and 2-bit parity cell data: Figure 1. The final correction is decided by comparing the parity checking results with the selected memory cell data. The (k+m)-bit memory cell data necessary for ECC is transfered to the parity generation circuits through a selector block for the appropriate 'decoding function. In the case of the proposed bidirectional parity checking technique, however, the column decoder for a multiplexer can also be used for a selector. Therefore, there is no need to prepare an additional decocler for memory cell selection. Since a single bit error per word line is correctable by introducing this ECC technique, the soft error rate of a high packing density RAM can be improved substantially, as shown in Figure 2. To accomplish high sensitivity without degrading operating speed, a threshold-difference compensated amplifier with capacitor-coupler presensing is proposed. Figure 3 shows an Organization 256K x 1 amplifier c rcuit and its operating waveforms. During the resetSupply voltage +5V single ting period, source nodes NC1 and Nc2 are precharged by clock 4kS to their own levels according to the threshold voltage of the flip flop transistors Q1 and Qz. In the sensing period, a flip flop Power consumption 200/3mW (active/standby) begins to detect the signal by clock @ ~ 1 . Since the source nodes are driven individually through coupling capacitors C1 and C2, the voltage difference between NC1 and Nc2 is almost equal Process technology to the reshold difference of the flip flop transistors at the beMo-gate (NMOS To,= 200 4 Leff=l.Op In developing VLSI memories that utilize a single transistor

Semiconductor dynamic memory device

Abstract: A semiconductor dynamic memory device includes a plurality of memories, row decoders for selecting the row of the memories, column decoders for selecting the column of memories, and sense amplifier circuits connected to the memories, respectively. The dynamic memory device further has a driving circuit for selectively activating some of the sense amplifier circuits in accordance with the content of a predetermined bit of row address data supplied to the row decoders.

Digital time delay circuit with high speed and large delay capacity

Abstract: A delay circuit including an even number of memory devices, for example two, reading from one memory device, while writing to the other. Sequences of bit addresses are generated for writing and reading, with an offset between the sequences. For the case of two memory devices, each address sequence is applied alternately to the one and then the other memory device. Importantly, if each memory device has an even number n of storage locations, then, preferably, only (n-1) of these are used in the generated sequences of addresses. This has the result that the circuit can write to and read from all of the memory locations in the memory devices. Thus, the maximum delay possible in the circuit of the invention is nearly the total number of bits in the multiple memory devices, and the circuit is capable of handling data at the maximum operating rate of the memory devices.

Dual stage sense amplifier for dynamic random access memory

Abstract: The present invention relates to the inclusion of an additional sense amplifier (100) on each column of a dynamic random access memory (RAM). The second sense amplifier is located near the input/output (DQ) line and functions to increase the rate of discharge of the selected column pair (Cn, Cn) thereby improving the transfer of logic information from a selected memory cell (M) to the input/output line associated therewith. The second sense amplifier in the column of the selected memory cell is activated by the same pulse (CCDQ) which connects the selected column to the input/output line, where only the second sense amplifier associated with the accessed column is activated during a single read/write cycle.

EPROM memory device having a test circuit

Abstract: An EPROM memory device includes a plurality of reprogrammable memory cells arranged in the form of a matrix and a test circuit capable of having two or more memory cells selected for operation at the same time during the test mode, to thereby reduce the required testing time significantly.

Video memory device

Abstract: A video memory device comprises an analog memory part in which memory elements are arranged in a matrix form with a plurality of rows and a plurality of columns, for storing an input analog video signal, an input circuit for applying the input analog video signal to the analog memory part and causing the analog memory part to store the input analog video signal, and an output circuit for obtaining an analog video signal delayed by a predetermined delay time from the analog memory part.

CMOS Sense amplifier

Abstract: A memory circuit comprises a plurality of memory cells and a plurality of sense circuits each including first and second input MOS transistors and first and second load MOS transistors of a first channel type and a load circuit connected to the sense circuit and including first to fourth load MOS transistors of a second channel type. The first and second input MOS transistors have their sources connected to each other and their gates connected to receive a differential input signal therebetween from said memory circuits of the first and second switching transistors which have their sources connected respectively to the drains of said first and second input transistors and their gates connected to a column selection signal. The first and second load MOS transistors have their drains connected in common to the drain of the first switching MOS transistors and their sources connected to each other. The third and fourth load MOS transistors have their drains connected in common to the drain of the second switching MOS transistors and their sources connected to each other. The gates of the first and fourth load MOS transistors are coupled respectively to the drains of the first and second switching MOS transistors, and the gates of the second and third load MOS transistors are cross-coupled to the drains of the second and first switching MOS transistors, respectively.

Semiconductor device with spare memory cells

Abstract: A semiconductor memory device includes a plurality of bit memory sections (BMS-1 to BMS-n), a plurality of column select circuits (14-1 to 14-n) for selecting columns of each of the bit memory sections, and one spare memory section (SMS-1, SMS-2). The spare memory section (SMS-1, SMS-2; SMS-11 to SMS-1 n) has spare memory cells of one column. The first switching circuits (20-1 to 20-n) are coupled with the column select circuits. A second switching circuit is coupled with the spare memory section (SMS-1, SMS-2). The semiconductor memory device further includes a control circuit (16-1, 16-2) programmable to operate in response to a specific address. When receiving the specific address, the control circuit turns off the selected one of the first switching circuits (20-1 to 20-n) and turns on the second switching circuit.

Memory device resistant to soft errors

Abstract: In a memory device, a plurality of memory cells are connected to bit line pairs. A precharge circuit is controlled by a chip enable signal during a stand-by state and by an address transition detector signal during an active state, to charge the bit line pairs up to a given power source voltage.

High-speed memory systems

Abstract: A highspeed, intelligent, distributed control memory system is disclosed. The system, according to the preferred embodiment of the invention, is comprised or an array or modular, cascadable, integrated circuit devices, hereinafter referred to as «memory elements». Each memory element is further comprised of storage means, programmable on board processing («distributed control») means and means for interfacing with both the host system and the other memory elements in the array utilizing a single shared bus. Each memory element of the array is capable of transferring (reading or writing) data between adjacent memory elements once per clock cycle. In addition, each memory element is capable of broadcasting data to all memory elements of the array once per clock cycle. This ability to asynchronously transfer data between the memory elements at the clock rate, using the distributed control, facilitates unburdening host system hardware and software from tasks more efficiently performed by the distributed control. As a result, the momory itself can, for example, perform such tasks as sorting and searching, even across memory element boundaries, in a manner which conserves, is faster and more efficient then using, host system resources.

Functional command for semiconductor memory

Abstract: A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit The memory circuit typically operates by receiving a plurality of defined operational signals which control data transfer to and from the memory circuit The method for initiating the selected functional mode comprises applying an active state of at least a first of the operational signals to the memory circuit followed by applying an active state of a second of the operational signals to the memory circuit The timing of the second operational signal relative to the first operational signal is not within the defined specification limits of the first and the second operational signals for conventional data transfer to and from the memory The step of applying the active state of the second operational signal, outside the defined limits, serves to initiate the selected functional mode for the memory circuit An example of the selected functional mode is the activation of circuitry (62) which serves to apply a predetermined data state to a redundant column (63) which can be substituted to replace a defective primary column within a memory array After the memory array has previously received a first data state and the circuit (62) is activated to apply a second data state to the redundant column (63) the memory array is read and each column which produces a second data state is determined to be a redundant column With knowledge of the column substitution algorithm, it can then be determined which of the redundant columns have been programmed to replace specific original columns This method can therefore determine the physical configuration of the memory circuit despite the incorporation of redundant elements into the primary memory array

SRAM with improved sensing circuit

Abstract: A static random access memory wherein positive feedback is used in the bit line loads. The output of the first sense amplifier stage is fedback to the gates of depletion-made bit line load transistors, to provide positive feedback during the read or write operation. That is, since one of the complementary bit lines which the accessed memory cell is attempting to pull down sees a load impedance which gradually becomes higher and higher, the memory cell can pull down this bit line more rapidly. To accomplish this with stability, the first sense amplifier stage has less than unity open loop gain, and a succeeding sense amplifier stage is therefore used for further amplification.

Complementary metal oxide semiconductor dual port random access memory cell

Abstract: Implemented as a monolithic integrated circuit in CMOS technology, consisting of two two-transistor inverters cross-coupled to form a four-transistor flip-flop memory cell plus an A port NMOS gating transistor connected to one side of the flip-flop and a B port NMOS transistor connected to the other side of the flip-flop. Each A port and B port gating transistor is respectively independently gated by an A port word line and a B port word line addressing signals to conduct the stored contents of the flip-flop respectively to an A port bit line or a B port bit line. The data signal upon each A port bit line and B port bit line is respectively independently gated through respective NMOS transistors by respective A port column address line and B port column address line addressing signals to next be individually compared, in a complementary sense, to a set reference voltage in a respective A port sense amplifier and B port sense amplifier. Reading from either or both the A and B ports is totally independent without conflict. Bit lines are preferably pulled up to the supply voltage. The sense line inputs to the A and B port sense amplifiers are also preferably pulled up to the supply voltage. Writing is by application of equal simultaneous addressing signals on both A and B ports plus the write enabled gating of complementary write data signals, representing the binary quantity to be stored, to each side of the flip-flop memory cell.

Resistor personalized memory device using a resistive gate fet

Abstract: A resistor personalized memory cell consisting of a resistive gate field effect transistor. One end of the gate electrode is connected to the memory cell access line, the other end to one of its source or drain regions. The source or drain region not connected to the gate electrode is connected to the memory cell bit line. Memory cell personalization is accomplished by selecting the resistance of the resistive gate. Memory cell data is read by detecting the current flow through the cell, the magnitude of the current flow being proportional to the gate resistance.

Redundant columns for byte wide memories

Abstract: Apparatus is provided for substituting a spare column of memory cells in a byte wide memory for a defective column of cells in such memory. The apparatus includes a spare column of memory cells, an electrically conductive line 13, a spare decoder 16 for switchably connecting the line 13 to the spare column, a first fuse FSD₁ between the spare column and the line 13, a series of second fuses FS controlling a series of switches T₁, T₂ . . . between the line 13 and corresponding sense amplifiers 11, and a series of third fuses FD, each connected between a corresponding column and the sense amplifier associated with that column. The spare column of memory cells is connected to the appropriate sense amplifier by blowing the appropriate fuse FS and supplying the necessary address information to spare decod­ er 16. The defective column of memory cells may be disconnected by blowing the appropriate fuse FD.

Programmable video display character control circuit using multi-purpose RAM for display attributes, character generator, and refresh memory

Abstract: A video display control circuit, for an intelligent terminal, includes a large cost efficient Random-Access Memory (RAM) A portion of the RAM memory is utilized as a high speed character generator instead of employing a dedicated Read Only Memory (ROM) Novel timing and memory control circuits are provided which permit characters to be generated witout any delay or change of real character timing The characters in RAM may be modified or changed which is not possible with dedicated Read Only Memories

Testing system for reliable access times in ROM semiconductor memories

Abstract: A testing circuit is disclosed for addressing and exercising a ROM-type memory and splitting the same memory output data into two paths. One path is used to temporarily hold the memory output data for a time-interval after which it is compared, in a digital comparator, with the same memory output data on the second path. When the data on both paths compare equally, then it is known that no instability has occurred during the time-interval. If a miscompare occurs, the comparator generates an error signal.

Sense amplifier circuit for semiconductor memories

Abstract: An improved sense amplifier circuit for sensing information in the cells of a semiconductor memory device is presented. The sense amplifier circuit as presented includes AC-coupled positive feedback means to provide a reduction in sensing delay time, and thus, faster memory access time.

Strip map memory controller

Abstract: A control apparatus for transferring characters from a font memory to a printer including a microprocessor which controls input and output of characters to and from a strip memory, tracks the status of input/output operations to insure overwriting of the memory does not occur, and supplies a minimal amount of control information to hardwired circuitry from which character building processes are autonomously controlled

Portable minicomputer for testing memories

Abstract: A portable high speed minicomputer tester is disclosed for isolating failures in a random access memory. The device includes a central processing unit having an address counter and means for generating a plurality of test words. Individual test words are generated automatically and stored in both an internal memory and the memory under test. At a predetermined address, a test word is read out of the memories and compared. If there are any discrepancies, the minicomputer sets a latch corresponding to the failed test word bit and identifies the failed bit on a digital display readout. Using fault conversion tables, an operator can trace a discrepancy to the bit location of a memory chip in the memory under test.

Multiple bit dynamic random-access memory

Abstract: A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations. Other innovations include an arbitration circuit, a hidden refresh function and unique accessing of redundant lines.

Static-type random-access memory device

Abstract: A static-type RAM device in which the amplitude of the data signal stored in a memory cell just after the writing in of data is completed is increased and the stability of the data stored in each memory cell is increased. The RAM device includes a bit-line pulling-up circuit for pulling up the potential of a bit line to a voltage which is approximately equal to or larger than the power supply voltage and a word-line pulling-up circuit for pulling up the potential of a selected word line to a voltage which is larger than the power supply voltage after the writing in of data is completed.

A battery backup 64K CMOS RAM with double-level aluminum technology

Abstract: A full CMOS 8K /spl times/ 8 bit RAM has been developed, incorporating a new circuit to transfer the memory automatically to the data-retention mode when supply voltage is lowered. For reducing operating power dissipation, internally synchronous circuits and a split power control technique were employed. A minimum cell size was obtained through the use of a double-level aluminum process.