Showing papers on "State (computer science) published in 2008"

Soft robotics: Biological inspiration, state of the art, and future research

Abstract: Traditional robots have rigid underlying structures that limit their ability to interact with their environment. For example, conventional robot manipulators have rigid links and can manipulate objects using only their specialised end effectors. These robots often encounter difficulties operating in unstructured and highly congested environments. A variety of animals and plants exhibit complex movement with soft structures devoid of rigid components. Muscular hydrostats e.g. octopus arms and elephant trunks are almost entirely composed of muscle and connective tissue and plant cells can change shape when pressurised by osmosis. Researchers have been inspired by biology to design and build soft robots. With a soft structure and redundant degrees of freedom, these robots can be used for delicate tasks in cluttered and/or unstructured environments. This paper discusses the novel capabilities of soft robots, describes examples from nature that provide biological inspiration, surveys the state of the art and outlines existing challenges in soft robot design, modelling, fabrication and control.

An Analysis of Active Learning Strategies for Sequence Labeling Tasks

Abstract: Active learning is well-suited to many problems in natural language processing, where unlabeled data may be abundant but annotation is slow and expensive. This paper aims to shed light on the best active learning approaches for sequence labeling tasks such as information extraction and document segmentation. We survey previously used query selection strategies for sequence models, and propose several novel algorithms to address their shortcomings. We also conduct a large-scale empirical comparison using multiple corpora, which demonstrates that our proposed methods advance the state of the art.

Data Refinement: Model-Oriented Proof Methods and their Comparison

Abstract: The goal of this book is to provide a comprehensive and systematic introduction to the important and highly applicable method of data refinement and the simulation methods used for proving its correctness. The authors concentrate in the first part on the general principles needed to prove data refinement correct. They begin with an explanation of the fundamental notions, showing that data refinement proofs reduce to proving simulation. The topics of Hoare Logic and the Refinement Calculus are introduced and a general theory of simulations is developed and related to them. Accessibility and comprehension are emphasized in order to guide newcomers to the area. The book's second part contains a detailed survey of important methods in this field, such as VDM, and the methods due to Abadi & Lamport, Hehner, Lynch and Reynolds, Back's refinement calculus and Z. All these methods are carefully analysed, and shown to be either imcomplete, with counterexamples to their application, or to be always applicable whenever data refinement holds. This is shown by proving, for the first time, that all these methods can be described and analyzed in terms of two simple notions: forward and backward simulation. The book is self-contained, going from advanced undergraduate level and taking the reader to the state of the art in methods for proving simulation.

Internet website traffic flow analysis

Abstract: An Internet-based analysis tool follows, in real-time, the flow of traffic through a website. For every website page requested by a website visitor, the state of the visitor's browser is recorded and data relating to the path visitors take through the website is collected and studied. The state of the visitor's browser path is maintained in a traffic analysis cookie that is passed between a website file server and the visitor browser with every page requested for viewing. The cookie is maintained in a size that can be passed from server to browser and back again without negatively impacting server performance and without negatively impacting browser performance. The data in the cookie can follow the visitor browser through independent file servers, regardless of how the pages of a website might be distributed in storage.

Deflating the big bang: fast and scalable deep packet inspection with extended finite automata

Abstract: Deep packet inspection is playing an increasingly important role in the design of novel network services. Regular expressions are the language of choice for writing signatures, but standard DFA or NFA representations are unsuitable for high-speed environments, requiring too much memory, too much time, or too much per-flow state. DFAs are fast and can be readily combined, but doing so often leads to state-space explosion. NFAs, while small, require large per-flow state and are slow.We propose a solution that simultaneously addresses all these problems. We start with a first-principles characterization of state-space explosion and give conditions that eliminate it when satisfied. We show how auxiliary variables can be used to transform automata so that they satisfy these conditions, which we codify in a formal model that augments DFAs with auxiliary variables and simple instructions for manipulating them. Building on this model, we present techniques, inspired by principles used in compiler optimization, that systematically reduce runtime and per-flow state. In our experiments, signature sets from Snort and Cisco Systems achieve state-space reductions of over four orders of magnitude, per-flow state reductions of up to a factor of six, and runtimes that approach DFAs.

Interactive locked state mobile communication device

Abstract: A mobile communication device receives current information while the mobile communication device is in one of a sleep state or a locked state, and associates one or more portions of the current information with one or more corresponding windows. The mobile communication device also displays, via a display associated with the mobile communication device, the one or more corresponding windows and the one or more associated portions of the current information while the mobile communication device is in the locked state. The mobile communication device further enables a user associated with the mobile communication device to manipulate the one or more displayed corresponding windows while the mobile communication device is in the locked state.

XFA: Faster Signature Matching with Extended Automata

Abstract: Automata-based representations and related algorithms have been applied to address several problems in information security, and often the automata had to be augmented with additional information. For example, extended finite-state automata (EFSA) augment finite- state automata (FSA) with variables to track dependencies between arguments of system calls. In this paper, we introduce extended finite automata (XFAs) which augment FSAs with finite scratch memory and instructions to manipulate this memory. Our primary motivation for introducing XFAs is signature matching in Network Intrusion Detection Systems (NIDS). Representing NIDS signatures as deterministic finite-state automata (DFAs) results in very fast signature matching but for several classes of signatures DFAs can blowup in space. Using nondeterministic finite-state automata (NFA) to represent NIDS signatures results in a succinct representation but at the expense of higher time complexity for signature matching. In other words, DFAs are time-efficient but space-inefficient, and NFAs are space- efficient but time-inefficient. In our experiments we have noticed that for a large class of NIDS signatures XFAs have time complexity similar to DFAs and space complexity similar to NFAs. For our test set, XFAs use 10 times less memory than a DFA-based solution, yet achieve 20 times higher matching speeds.

Computer resource distribution method based on prediction

Abstract: A resource distribution method capable of lending surplus resources among a plurality of services and reducing the maintenance cost of the surplus resources is provided. Computer resources in the standby system have a dead standby state in which at least an application is not installed. A plurality of services or a plurality of users share the computer resources in the standby system. As a result, improvement of the utilization factor of idle computer resources and server integration are implemented, and the cost required to maintain the computer resources is reduced. Furthermore, load prediction is conducted as regards individual services by using past operation history. Idle computer resources secured from services having surplus and maintained are thrown in according to a result of the prediction.

An improved DFA for fast regular expression matching

Abstract: Modern network devices need to perform deep packet inspection at high speed for security and application-specific services. Finite Automata (FAs) are used to implement regular expressions matching, but they require a large amount of memory. Many recent works have proposed improvements to address this issue.This paper presents a new representation for deterministic finite automata (orthogonal to previous solutions), called Delta Finite Automata (δFA), which considerably reduces states and transitions and requires a transition per character only, thus allowing fast matching. Moreover, a new state encoding scheme is proposed and the comprehensive algorithm is tested for use in the packet classification area.

Transitioning a processor package to a low power state

Abstract: A processor package is controlled to be in a package low power state for a first portion of an operation interval and in a package active state for a second portion of the operation interval. To enable the low power state, operations scheduled during the first portion are delayed until the second portion.

Disk drive comprising a trellis detector having a read signal whitener in the ACS circuit

Abstract: A disk drive is disclosed comprising a disk, a head actuated over the disk to generate a read signal, and a trellis detector for detecting an estimated data sequence from the read signal. The trellis detector comprises a sampling device operable to sample the read signal to generate a sequence of signal sample values, and a plurality of add/compare/select (ACS) circuits each corresponding to a state in a trellis. Each ACS circuit comprises a first and second branch metric calculators for computing first and second branch metrics in response to first and second errors adjusted in response to first and second deltas that compensate for a distortion in the read signal.

Multi-state unified pie user interface

Abstract: A state menu selection system that provides a function control set relating to an active application, maps at least one function from the function control set to at least one input device, and activates a function from the control set upon activation of the corresponding input device.

Managing data delivery based on device state

Abstract: Managing power-consuming resources on a first computing device by adjusting data delivery from a plurality of second computing devices based on a state of the first computing device. The state of the first computing device is provided to the second computing devices to alter the data delivery. In some embodiments, the first computing device provides the second computing devices with actions or commands relating to data delivery based on the device state. For example, the second computing devices are instructed to store the data, forward the data, forward only high priority data, or perform other actions. Managing the data delivery from the second computing devices preserves battery life of the first computing device.

Spectral Logic and Its Applications for the Design of Digital Devices

Abstract: PREFACE. ACKNOWLEDGMENTS. LIST OF FIGURES. LIST OF TABLES. ACRONYMS.1. LOGIC FUNCTIONS. 1.1 Discrete Functions. 1.2 Tabular Representations of Discrete Functions. 1.3 Functional Expressions. 1.4 Decision Diagrams for Discrete Functions. 1.5 Spectral Representations of Logic Functions. 1.6 Fixed-polarity Reed-Muller Expressions of Logic.Functions. 1.7 Kronecker Expressions of Logic Functions. 1.8 Circuit Implementation of Logic Functions. 2. SPECTRAL TRANSFORMS FOR LOGIC FUNCTIONS. 2.1 Algebraic Structures for Spectral Transforms. 2.2 Fourier Series. 2.3 Bases for Systems of Boolean Functions. 2.4 Walsh Related Transforms. 2.5 Bases for Systems of Multiple-Valued Functions. 2.6 Properties of DiscreteWalsh andVilenkin-Chrestenson Transforms. 2.7 Autocorrelation and Cross-Correlation Functions. 2.8 Harmonic Analysis over an Arbitrary Finite Abelian Group. 2.9 Fourier Transform on Finite Non-Abelian Groups. 3. CALCULATION OF SPECTRAL TRANSFORMS. 3.1 Calculation of Walsh Spectra. 3.2 Calculation of the Haar Spectrum. 3.3 Calculation of the Vilenkin-Chrestenson Spectrum. 3.4 Calculation of the Generalized Haar Spectrum. 3.5 Calculation of Autocorrelation Functions. 4. SPECTRAL METHODS IN OPTIMIZATION OF DECISION DIAGRAMS. 4.1 Reduction of Sizes of Decision Diagrams. 4.2 Construction of Linearly Transformed Binary Decision Diagrams. 4.3 Construction of Linearly Transformed Planar BDD. 4.4 Spectral Interpretation of Decision Diagrams. 5. ANALYSIS AND OPTIMIZATION OF LOGIC FUNCTIONS. 5.1 Spectral Analysis of Boolean Functions. 5.2 Analysis and Synthesis of Threshold Element Networks. 5.3 Complexity of Logic Functions. 5.4 Serial Decomposition of Systems of Switching Functions. 5.5 Parallel Decomposition of Systems of Switching Functions. 6. SPECTRAL METHODS IN SYNTHESIS OF LOGIC NETWORKS. 6.1 Spectral Methods of Synthesis of Combinatorial Devices. 6.2 Spectral Methods for Synthesis of Incompletely Specified Functions. 6.3 Spectral Methods of Synthesis of Multiple-Valued Functions. 6.4 Spectral Synthesis of Digital Functions and Sequences Generators. 7. SPECTRAL METHODS OF SYNTHESIS OF SEQUENTIAL MACHINES. 7.1 Realization of Finite Automata by Spectral Methods. 7.2 Assignment of States and Inputs for Completely Specified Automata. 7.3 State Assignment for Incompletely Specified Automata. 7.4 Some Special Cases of the Assignment Problem. 8. HARDWARE IMPLEMENTATION OF SPECTRAL METHODS. 8.1 Spectral Methods of Synthesis with ROM. 8.2 Serial Implementation of Spectral Methods. 8.3 Sequential Haar Networks. 8.4 Complexity of Serial Realization by Haar Series. 8.5 Parallel Realization of Spectral Methods of Synthesis. 8.6 Complexity of Parallel Realization. 8.7 Realization by Expansions over Finite Fields. 9. SPECTRAL METHODS OF ANALYSIS AND SYNTHESIS OF RELIABLE DEVICES. 9.1 Spectral Methods for Analysis of Error Correcting Capabilities. 9.2 Spectral Methods for Synthesis of Reliable Digital Devices. 9.3 Correcting Capability of Sequential Machines. 9.4 Synthesis of Fault-Tolerant Automata with Self-Error Correction. 9.5 Comparison of Spectral and Classical Methods. 10. SPECTRAL METHODS FOR TESTING OF DIGITAL SYSTEMS. 10.1 Testing and Diagnosis by Verification of Walsh Coefficients. 10.2 Functional Testing, Error Detection, and Correction by Linear Checks. 10.3 Linear Checks for Processors. 10.4 Linear Checks for Error Detection in Polynomial Computations. 10.5 Construction of Optimal Linear Checks for Polynomial Computations. 10.6 Implementations and Error-Detecting Capabilities of Linear Checks. 10.7 Testing for Numerical Computations. 10.8 Optimal Inequality Checks and Error-Correcting Codes. 10.9 Error Detection in Computer Memories by Linear Checks. 10.10 Location of Errors in ROMs by Two Orthogonal Inequality Checks. 10.11 Detection and Location of Errors in Random-Access Memories. 11. EXAMPLES OF APPLICATIONS AND GENERALIZATIONS OF SPECTRAL METHODS ON LOGIC FUNCTIONS. 11.1 Transforms Designed for Particular Applications. 11.2 Wavelet Transforms. 11.3 Fibonacci Transforms. 11.4 Two-Dimensional Spectral Transforms. 11.5 Application of the Walsh Transform in Broadband Radio. APPENDIX A. REFERENCES. INDEX.

Resistance change nonvolatile memory device

Abstract: A selection circuit that selects a memory cell from a memory cell array and a read circuit for reading a resistance state of a resistance change element in the selected memory cell are provided. In memory cells of odd-numbered-layer and even-numbered-layer memory cell arrays that constitute a multilayer memory cell array, each memory cell in any of the layers has a selection element, a first electrode, a first resistance change layer, a second resistance change layer, and a second electrode that are disposed in the same order. Whether the selected memory cell is located in any layer of the multilayer memory cell array, the read circuit applies a voltage to the selected memory cell to perform the reading operation. The voltage applied to the selected memory cell causes the second electrode to become positive with reference to the first electrode in the selected memory cell.

Remote attestation on program execution

Abstract: Remote attestation provides the basis for one platform to establish trusts on another. In this paper, we consider the problem of attesting the correctness of program executions. We propose to measure the target program and all the objects it depends on, with an assumption that the Secure Kernel and the Trusted Platform Module provide a secure execution environment through process separation. The attestation of the target program begins with a program analysis on the source code or the binary code in order to find out the relevant executables and data objects. Whenever such a data object is accessed or a relevant executable is invoked due to the execution of the target program, its state is measured for attestation. Our scheme not only testifies to a program's execution, but also supports fine-granularity attestations and information flow checking.

Generating device-specific configurations

Abstract: An approach to generating device-specific configurations is described In one approach, a method of generating a device-specific configuration for a target device is described The method involves receiving a configuration parameter, and receiving command syntax information A state description is generated from the configuration parameter, with reference to a configuration library Device information is retrieved from the target device, and the device-specific configuration is generated with reference to the command syntax information, the device information, the state description, and a command library

Efficient Stateful Dynamic Partial Order Reduction

Abstract: In applying stateless model checking methods to realistic multithreaded programs, we find that stateless search methods are ineffective in practice, even with dynamic partial order reduction (DPOR) enabled. To solve the inefficiency of stateless runtime model checking, this paper makes two related contributions. The first contribution is a novel and conservative light-weight method for storing abstract states at runtime to help avoid redundant searches. The second contribution is a stateful dynamic partial order reduction algorithm (SDPOR) that avoids a potential unsoundness when DPOR is naively applied in the context of stateful search. Our stateful runtime model checking approach combines light-weight state recording with SDPOR, and strikes a good balance between state recording overheads, on one hand, and the elimination of redundant searches, on the other hand. Our experiments confirm the effectiveness of our approach on several multithreaded benchmarks in C, including some practical programs.

Parking lot booking system and its use method

Abstract: This system consists of a car position tester (CPT) and a car position managing server (CPS). CPS consists of the position managing module, the idle position judging module (EPJ), the position inquiry module, the position preserving module (PP) and the position preservation charging module. Steps of using this system include: 1) numbering the positions; 2) CPT sending position state info to EPJ; 3) real-time judging position idle state; 4) the position preservation terminal (PPT) sending the position inquiry instruction to CPS; 5) PPT obtaining the inquiry result and sending the position preservation info; 6) PP preserving the position and sending the preservation result to PPT. This technical scheme records accurately all position idle states of the parking lot and forecasts the position state changing. This raises the utilization of car position resource and reduces the cost of car using.

Semiconductor integrated circuit

Abstract: A semiconductor integrated circuit includes a core circuit, a power supply switch situated on a path providing a current to the core circuit and configured to control a state of current supply to the core circuit in response to a control signal applied to a control node, a clamp circuit configured to clamp a voltage of the control signal, and a switching circuit configured to control whether to enable or disable a clamp operation of the clamp circuit.

Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states

Abstract: A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f)R. The logic “1” state is represented by a mathematical expression (n+f)R. The logic “2” state is represented by a mathematical expression (1+nf)R. The logic “3” state is represented by a mathematical expression n(1+f)R.

Network processor power management

Abstract: A programmable state machine is incorporated into the core of a network processor (NP) to monitor the utilization of different processing elements in the NP and to control the power state of each element as a function of past and predicted utilization. The state machine can be used to control a centralized power management control unit or to control a distributed power management unit where each processing element includes its own state machine. The function of the power management state machine can be implemented in any combination of software and/or hardwired logic, depending on the system design requirements. The monitoring and control are implemented through the use of a power management state change algorithm. The determination of the power state of a processing element accommodates interdependencies between the elements. It also makes adjustments in gain factors in response to actual performance and utilization of the network processor.

Power management mode aware mesh beacon collision avoidance and information update mechanism

Abstract: Apparatus, methods and computer program products provide power management mode aware mesh beacon collision avoidance and information update mechanisms at a first mesh point in a wireless mesh network. The information update mechanism operates by detecting that a timing-related beacon transmission parameter of the first mesh point has changed; generating a message containing updated timing-related beacon transmission parameter information for the first mesh point; determining when a second mesh point operating in a power saving mode will transition to an awake state; and transmitting the message containing the updated timing-related beacon transmission information during a time corresponding to the awake state of the second mesh point.

Decrease-radix design principle for carrying/borrowing free multi-valued and application in ternary optical computer

Abstract: In this paper a new theory referred to as the decrease-radix design (DRD) is proposed, which is found in the research of logic units of ternary (tri-valued) optical computer. Based on the theory proposed, the principles and the regulations of the DRD for making operation units of multi-valued operation with carrying/borrowing free are also presented. The research work has come to the following important conclusion: let D be a special state contained in n physical informative states, then one may figure out any multi-valued processors within n (n×n) carrying/borrowing free n-valued units by the composition some of n×n×(n−1) simplest basic operating units according to the regulations of DRD proposed in this paper. The detailed systematic way of our design regulations is highlighted step by step in the paper with an example of design of a tri-valued logic optical operating unit. The real architecture, the procedure, and the experimental results of our sample in tri-valued logic operating unit are given. Finally, a re-constructible model of ternary logical optical processor is introduced. The theory proposed in the paper has laid down a solid foundation for the design of re-constructible carrying/borrowing free operating units in ternary optical computers and can be widely used as the designing reference in a variety of multi-valued logic operating units.

Semiconductor memory device

Abstract: PURPOSE:To effectively utilize a memory cell by providing a means to prohibit reading of information from an arbitrary pair of memory cell blocks out of the memory cell blocks and to transmit information in the remained pairs of the memory cell blocks to an output terminal. CONSTITUTION:When an output line 72 is turned to an active state by the preserved information of internal program circuits 61-68, a block selecting circuit 71 makes a sense amplifier output line 31 and a data output line 81 not- conducted by the operation of a replacing circuit 41 and a sense amplifier output line 39 and a data output line 89 are turned to a conducting state through a selecting data line. Instead of a memory cell array 1, the data of a memory cell array 9 are outputted to the data output line 89 and 8 bits are read out. Accordingly, in the case of 8 bit constitution caused by the semiconductor memory device of 9 bits, for example, since the memory cell array, which is not used, is exchanged with the memory cell array generating operational trouble, the semiconductor memory device with 8 bit constitution can be obtained. Thus, the memory cell array can be effectively utilized.

Telemetry during safety mode operation

Abstract: This document discusses, among other things, n implantable device comprising a communication circuit configured to communicate with an external device, a logic circuit communicatively coupled to the communication circuit, and a processor, communicatively coupled to the logic circuit and the communication circuit. The processor is configured to communicate information with the external device, via the communication circuit and the logic circuit, using a set of communication messages. While in a device safety mode, the processor is held in an inactive state and the logic circuit is configured to communicate with the external device using a subset of the set of communication messages.

State-sensitive navigation aid

Abstract: Navigation logic and related methods are described for assisting a user in using a remote control (RC) device. The navigation logic determines a current state of a user's interaction with an application, and then determines the keys of the RC device that are relevant to the determined state. The navigation logic then displays a representation of the relevant keys on a user interface presentation of a presentation device. The representation resembles a physical layout of associated physical keys on the RC device. To assist the user in focusing on the relevant keys, the representation de-emphasizes other input mechanisms of the RC device that do not have a bearing on the user's current interaction with the application. One exemplary way of de-emphasizing these other keys is to entirely omit these keys from the representation.