Showing papers on "Transmission delay published in 1980"

Analysis of a Two-Hop Centralized Packet Radio Network--Part I: Slotted ALOHA

Abstract: The design of packet radio systems involves a large number of design variables that interact in a very complex fashion. As this design problem in its general form is quite complex, a viable approach is to analyze some simple but typical configurations in an attempt to understand the behavior of these systems. In this paper, a two-hop centralized configuration is considered in which traffic originates at terminals, is destined to a central station, and requires for its transport the relaying of packets by store-and-forward repeaters. The through-put-delay performance is derived, and its dependence on such key system variables as the network topology, the transmission protocol, and the repeaters' storage capacities, is given. In this part, devices are assumed to be utilizing the slotted ALOHA access mode. Carrier sense multiple access is treated in Part II of this series [1].

Analysis and Optimal Design of a Packet-Voice Receiver

Abstract: The analysis problems arising from a digital packet switched speech network are outlined in a wide statistical environment. The statistical models assumed are discussed with respect to practical applications. Particular attention is devoted to a formal description of the influence of the packet voice receiver on the system behavior in terms of the delay pdf. The optimization of the system performance, in order to obtain the best voice quality, is stated as an optimal control problem, and the analysis results play a central role in the construction of the objective functions. The problem is solved in a particular analytical environment. The outlined analytical results are supported by critical comments on their comparison with practical implementations, allowing the designer a better capability in handling any problems.

A new class of protocols for multiple access in satellite networks

Abstract: In this paper, a class of multiple access schemes is introduced, especially suited for use in packet switched satellite networks. These schemes, called the Interleaved Frame Flush-Out (IFFO) protocols, are characterized by the mixing of free contention and regulated access for the use of the satellite channel. Such hybrid schemes possess desirable features of both extreme strategies and have a built-in capability to adapt to the traffic load profile. A Markov chain model is introduced for their description and analysis, and an optimization problem is formulated for choosing the "best" among the members of this class of protocols. The performance of the protocols is evaluated by computation and simulation, and comparison to other protocols. It is shown to be stable and superior to that of the other protocols over a wide range of throughput values.

A Tradeoff Study of Switching Systems in Computer Communication Networks

Abstract: This paper is concerned with a comparison study of three switching techniques used in computer-based communication networks: circuit switching, message (packet) switching, and cut-through switching. Our comparison is based on the delay performance as obtained through analytic models of these techniques. For circuit switching, the model reflects the phenomenon of channel reservation through which it can be shown that when circuit switching is used, data communication networks saturate rapidly. Through numerical examples, it is shown that the boundary between the areas of relative effectiveness of these switching techniques depends very much on the network topology (more precisely the path length of communication), the message length, and the useful utilization.

Deadlock- and livelock-free packet switching networks

Abstract: A controller for a packet switching network is an algorithm to control the flow of packets through the network. A local controller is a controller executed independently by each node in the network, using only local information available to these nodes. A controller is deadlock- and livelock-free if it guarantees that every packet in the network reaches its destination within a finite amount of time. We present a local controller which is proved to be deadlock- and livelock-free.

Computer-communications concentrator for transmission and switching of packetized data

Abstract: A computer-communications concentrator for establishing connections between a plurality of asynchronous computer-communications terminals and a two-way computer-communications channel for transmission and switching of packetized data. The concentrator is comprised of one processing unit which is operated asynchronously and is connected to the computer-communications terminals. One X25 interface normalizing function processing unit is connected to the two-way computer-communication channel, with, between the two processing units, a communication system comprised of one memory unit having a first part in which each packet transmitted in one or the other direction is stored, and a second part comprised of forward and return cell pairs. Each cell is provided to store a packet header during a transfer into the communication system, each local header containing the address of the packet stored in the first part of the memory unit, its length, and some data relevant to the type of packet, the interpretation of which is used to determine in the processing unit which reads it, the appropriate processing to be done for the packet at hand. Each link between a terminal and the two-way channel makes use of a couple of selected pairs of cells, each packet being stored in a location available from the first part of the processing unit which introduces this packet into the memory inserting a local header in the corresponding outgoing cell from the associated cell pair, then transferring this local header into the return cell of the other pair from the set associated with the unit which will output the packet from the memory unit when this cell is available as indicated by a particular value of the packet type information.

Analysis of a Two-Hop Centralized Packet Radio Network--Part II: Carrier Sense Multiple Access

Abstract: We continue in this paper our study of two-hop centralized packet radio networks in view of understanding the behavior of these systems. Traffic originates at terminals, is destined to a central station, and requires for its transport the relaying of packets by store-and-forward repeaters. We consider here that all devices employ the nonpersistent carrier sense multiple-access mode. System capacity and through-put-delay tradeoffs are derived and compared to those obtained for slotted ALOHA in Part I [l].

Voice/Data Integration Using Circuit Switched Networks

Abstract: This paper assesses the impact of integrating voice and data over circuit switched networks. Three main types of circuit switching are considered: 1) traditional circuit switching, 2)fast circuit switchingemploying advanced switching speeds, and 3) enhanced circuit switchingemploying time assigned speech interpolation (TASI) and adaptive data multiplexing (ADM) techniques. The circuit switching networks are evaluated in terms of two main network performance parameters: transmission efficiency and delay. In addition, an evaluation is made of such things as protocol and error control, precedence and preemption, routing and flow control, synchronization, voice continuity, probability of error or loss, and classmarking flexibility. One of the main conclusions of this paper is that circuit switching technologies have several deficiencies associated with providing integrated voice/data service and that the future lies in the effective use of packet and hybrid (circuit/packet) switching technologies.

Reaction time measurement errors resulting from the use of CRT displays

Abstract: Three sources of potential error in reaction time measurement may occur when raster scan CRT displays are used to present stimuli: phosphor persistence, sweep delay, or transmission delay. For most applications, only the third source of error is likely to be significant.

Delta Modulators in Packet Voice Networks

Abstract: In this paper, the performances of the Song Voice Adaptive Delta Modulator (SVADM) and the Continuously Variable Slope Delta Modulator (CVSD) in terms of dynamic range, sampling rate and the channel errors are compared. The use of the SVADM and the CVSD in a packet voice system, the algorithms for digital detection of silent periods and the performance of a packet voice system using the SVADM and the CVSD as source encoders are presented. The parameters employed for subjective evaluation of the packet voice system are packet size, silence detection algorithm, bit rate and packet loss rate.

Signal transmission system

Abstract: PURPOSE:To make the same clock unnecessary to the whole system and to make it possible to avoid an error based on transmission delay by use of a simple device, by checking transmission delay with the repeating installation only CONSTITUTION:When the transmission line 2 into which the repeating installation 3 has been inserted is commonly used by several signal generation device 1, and there exists a signal input exceeding the transmission capacity of the transmission line 2, the overflowing signal is stored in the buffer memory 21 of the device 3 and is made to wait, while the device 1 performs retransmission or demand unless there is a response within a given period of time And when the delay time from input to output to the device 3 is a signal exceeding the fixed value, or the time until the signal reaches one device 1 from the other device 1 is less than the fixed value, comparing with the time to transmit the signal to the other device 1 from one device 1, the latter signal is abandoned Thus the same clock can be made unnecessary to the whole system, and the error based on transmission delay can be avoided by use of a simple device

Integrated Voice/Data Packet Switching Techniques for Future Military Networks

Abstract: Virtual circuit and pure packet (datagram) based switching techniques are studied for future application to the integrated voice/data telecommunications. The coexistence of voice with both interactive and bulk data in an integrated network suggests the desirability of a mixed switching technique to allow the efficient sharing of both the switching and communications resources. Such a mixed packet switching scheme is also evaluated. It uses virtual circuit for regular traffic (voice and bulk data), and uses pure packet (datagram) for bursty traffic (interactive and query/response). It also adapts to changes in voice/ data input traffic mixture.

The DIMOND: A Component for the Modular Construction of Switching Networks

Abstract: The DIMOND is a building block for communication networks in which throughput is more important than transmission delay. Its main attraction stems from the fact that it allows the routing of messages through a network to be completely distributed over the individual building blocks.

Message Waiting Time in a Packet Switching System

Abstract: The behavior of a buffer having an arbitrary number of common output channels in a packet switchmg system with an arbitrary number of priority classes of messages as studied Because of the random lengths of the messages and the fixed packet size, some messages must be split into several packets. Packets of the same message may not be sent immediately m sequence because of the packets of higher priority messages Therefore, the message wamng tame is defined as the wamng tame of the last packet carrying a part of the given message The hmmng probability dastnbution of thas delay is calculated for the case of mdependent packet amval processes wRh stataonary independent increments Some numerical results are also presented The results obtamed can be used m the analysis of message path delay in certain store-and-forward commumcatton systems, particularly loop communication systems.

A Simple Model for Computation of Packet Radio Network Communication Performance

Abstract: A model is presented that allows the computation of the approximate level of communication performance for an arbitrary packet radio network using one of a variety of protocols. The communication performance is specified in terms of the end-to-end message delays incurred for a given level of end-to-end traffic rates. The network is specified in terms of its link capacities. While the model makes a variety of assumptions to allow simple computation of the performance level, agreement within a factor of two is obtained with results from simulation. As the number of nodes in the network and its connectivity is increased, the model is expected to give better accuracy. Thus, the model should prove to be a useful tool in the design and analysis of large packet radio networks where detailed analysis and simulation would prove too cumbersome.

Control system for transmission of confirmation packet on loop transmission line

Abstract: PURPOSE:To improve the use efficiency of a loop transmission line, by controlling the transmission time of a confirmation packet CONSTITUTION:When a CPU3 designates a destination and requests a communication control device 4 to transmit a confirmation packet, a destination discriminating processing part 6 of the device 4 inspects the type of a subsystem to which the confirmation packet should be transmitted, and the inspection result is sent to a confirmation packet transmission time calculating part 7 The calculating part 7 calculates a time from the data packet transmission to the confirmation packet transmission on a basis of destination discrimination information, and after the calculated time from the time of the data packet transmission, the calculating part 7 requests a confirmation packet output part 8 to transmit the confirmation packet The confirmation packet from the output part 8 is transmitted onto a loop transmission line 2 through a highway control part 9

Method and device for speech signal reconstruction in packet switched telecommunication networks

Abstract: The disturbing effects caused by the random delay suffered by the packets in the network are reduced by preventing the first packet of each talkspurt from suffering a random delay lower than a predetermined minimum delay. To this end the delay suffered by the first packet of a talkspurt is estimated and the packet is stored, before being introduced into the output queue of the node, for a time depending on the estimated delay. The delay estimate is made to converge to the actual value by a progressive synchronization of source and receiver clocks.

Distribution of Packet Delay and Interdeparture Time in Carrier Sense Multiple Access.

Abstract: : Existing analysis of the carrier sense multiple access mode (CSMA) has led to the determination of the average channel performance in terms of average throughput and average packet delay. This was achieved by formulating a semi-markovian model for CSMA channels with a finite population of users. In this paper, it is shown that, using the same model, it is possible to derive the actual packet delay distribution. The analysis is similar in nature to that provided for slotted ALOHA channels. These results are useful in the design of systems intended for real time applications such as digitized speech, and in the analysis of multihop packet radio systems. (Author)

Microprocessor Utilization in Satellite-Born Packet Switching

Abstract: This correspondence deals with the application of a bit slice microprocessor to a satellite born packet switch. A system architecture for accomplishing this task is proposed, and the performance of the packet switch is evaluated by obtaining an upper bound on the system throughput.

Interrframe transmission phase switching system

Abstract: PURPOSE:To facilitate an easy increment and extension of the transmission system by giving the switching and correction to the transmission delay amount in accordance with the installation distance between the master and slave devices CONSTITUTION:The long-distance or short-distance transmission is decided according to the distance between the master and slave devices And for the long-distance transmission from master device PE, the information transmitted at the same time of the A-series clock such as A0 is received at each slave device CE at the different time of the B-series (long distance (a), short distance (b)) Then with the different set delay amount, for example, with delay of T second in the case of the long distance and 2T seconds in the case of the short distance each, the information is taken into device CE at the same time such as C3 of the C-series clock And the vice versa for the transmission carried out from the slave to master station Thus the delay amount is switched according to the distance between the master and slave devices, thus facilitating the system extension

Delay line compensation network

Abstract: OF THE DISCLOSURE A timing generator circuit includes a pair of multi-tap cascaded delay lines of like construction. Each delay line includes a plurality of sections each of which are constructed to provide the same increment of delay at each tap. A capacitive element connects between prede-termined taps of the two delay lines to form a compensa-tion network including a predetermined section of each delay line. The compensation network which operates to cancel out the effects of any mismatch resulting from connecting the delay lines in series.

Switching system for transmission line

Abstract: PURPOSE:To have measurement via the timer for the transmission delay amount of the switching office section when the control signal to perform the switching is transferred among the switching office sections and then to decide the switching timing based on the measured value, thus eliminating the dispersion of the process time for the switch control information. CONSTITUTION:The connection is secured among switching offices A-D via information control wire 1 which transmits the switch control information along with transmission line 2 including several pieces of systems. Then control information transmission and reception parts 13 and 14 which perform the transfer of the control information among offices A-D and other offices are provided along with the transmission line fault detection interface and transmission line change-over switch part 16 which perform the switching of transmission line 2. Furthermore, switch control part 11 is provided to give the decision based on the information given from parts 14 and 16, send out the necessary control information from part 13 and also indicate the necessary swithing to part 16, along with timer circuit 12 which measures the information transmission time to the remote office. Thus the dispersion can be eliminated for the process time.

Function testing system for communication control unit

Abstract: PURPOSE:To secure the function test with the single unit of the communication control unit by installing within the communication control unit the clock oscillator of the same frequency as the clock of the monitor device plus the delay memory featuring the equal time to the loop transmission delay time each. CONSTITUTION:When the single unit test mode is designated through the control panel, the clock sent from clock oscillation circuit 8 in the communication control unit is supplied to each part in place of the clock which is sent from the monitor device to repeater 2 via transmission line 1. And the data from control part 4 is sent to transmission part 5 via frame buffer memory 7. The data of the serial bits sent from part 5 is supplied to reception part 3 and then returned to part 4 again. As the delay time of memory 7 is equal to the loop delay time on the transmission line, the artifitial loop is formed within the communication control unit. Thus the data read out of memory 7 can be seen as if it were just on the transmission line. As a result, each block within the communication control unit features nearly the same operation as that of the normal operation, thus enabling the test with the single unit.

Time sharing communication line system

Abstract: PURPOSE:To simplify the constitution of communication line of small capacity applicable to small sized station without changing the timing circuit, by omitting a part of the time sharing switch of the multiple-stage link circuit and replading it to the delay circuit. CONSTITUTION:When the large scale time sharing communication line constituting the multiple link circuit (n stages) using a plurality of time switches as exchanger function element to the small sized station, the switch module M1 constituting the multiple switch circuit consists of the multiplex circuit 1 constituting the multi-stage link circuit, communication memory 2, separation circuit 3 and hold memory 4 and delay circuit 5. Further, the multi-stage link circuit is taken as m-stages, the delay circuit 5 is located in place of the link circuit omitted, the transmission delay difference between the input phase of prestage and that of post stage is compensated at the delay circuit 5, to simplify the time sharing communication line.

Control system for transmission delay variation

Abstract: PURPOSE:To enable to absorb the transmission delay variation in the digital communication system performing time sharing multiplex transmission in block unit, at the reception side, by providing given circuits respectively. CONSTITUTION:The memory TSM storing the information in block unit, memory taking the block number as the address and writing in the information storage address of the memory TSM, and the memory M2 transferring and storing this content, are respectively provided. Further, the counter CNT2 controlling the transfer from the memory M1 to M2 by counting the clock at the reception side is provided. Further, the difference between the number VCNn of the fill-in synchronous block transmitted when the no waiting for the buffer at the transmission side is made, and the value corresponding to the time greater than the maximum delay time of the information from the transmission section to the reception section is set to the counter CNT2. Next, the count content is taken as the transfer address from the memory M1 to M2 and the content of the memory M2 is taken as the readout address of the memory TSM. Thus, the delay variation in information can be absorbed.

Short circuit protection system for railway power transmission lines - uses testing pulse control with delay system controlling switching operations

Abstract: The control system for protecting equipment receiving power from an overhead transmission line includes an automatic system of testing and return switching, giving protection against short circuits. A control unit in one section generates control pulses to operate a system of flip-flops, and has a ring counter, an oscillator, a binary counter and a set of switches. These connect to a decoder in the branch section. A delay system blocks switching action, if a fault is detected. The transmission line section being tested is cut out, if there is a fault during the delay period included during a test for return switching, due to the operation of the flip-flops.