Showing papers on "Wafer published in 1971"

Fabrication of semiconductor devices having low thermal inpedance bonds to heat sinks

Abstract: A layer of contact metallization is applied over the surface of a semiconductor slice having a P-N junction. A heat sink layer of high conductivity metal, such as copper, is applied over the contact metallization with a sufficient thickness to provide a predetermined heat dissipation for the P-N junction. A plurality of spaced apart discrete metal contacts are formed over the opposite surface of the semiconductor slice. Portions of the semiconductor slice are then removed between the metal contacts in order to form an array of discrete semiconductor devices, such as avalanche diodes, extending from the heat sink layer. The heat sink layer is then divided to provide a plurality of semiconductor devices attached to individual low thermal impedance heat sink members.

Mounting block for semiconductor wafers

Abstract: A mounting block carries a processed semiconductive wafer through subsequent steps, i.e., dicing, cleaning, testing and chip selection. The mounting block has a raised circular central portion to which the wafer is bonded by means of an adhesive. The central portion contains a plurality of apertures, each corresponding to and to be in registry with a device in the wafer to be mounted thereon. The apertures enable the wafer to be secured to the block without touching the device surface, by applying a vacuum to the backside. The apertures also permit later removal of only acceptable chips from the mounting block without loss of orientation. The central portion is also slotted to permit wafer to be diced without the blades touching the block surface or adhesive, whereby the block may be repeatedly reused and the blade has longer life. A lower circuit flange on the block is provided with a notch and flats, for alignment purposes using apparatus for mounting the wafer in precise alignment including a microscope. The mounting block is also supported in one of several saws.

Apparatus for the automatic alignment of two superimposed objects, e.g. a semiconductor wafer and mask

Abstract: An apparatus for automatically aligning a semiconductor wafer with a mask in the manufacture of integrated circuit devices is disclosed. The mask and wafer are each provided with alignment patterns, the alignment pattern on the wafer cooperating with the alignment pattern on the mask in a unique visual mannner to signify alignment. A scanning mechanism is provided for automatically scanning the alignment pattern areas and producing output signals indicative of the relative positions of the alignment patterns on the wafer and mask. Logic circuitry is provided for operating in response to any misalignment represented by the scan output signals to compute formulae which are utilized to produce control signals for driving motor drive mechanisms to produce relative movement between the mask and wafer to bring them into alignment. Several separate alignment cycles are provided, if needed, for zeroing in on finalized alignment. A tolerance selection control circuit is provided for permitting a variation in final alignment tolerance.

Optical alignment method and apparatus

Abstract: An electro-optical mask and wafer alignment system employs alignment patterns on the mask and wafer whose images can be selectively passed through a spatial filter. Each pattern comprises at least two nonparallel lines. The alignment pattern configuration permits the X, Y coordinate locations of at least two corresponding points on the mask and wafer to be sensed by scanning the filtered images of the alignment patterns past a sensing device in a single direction. The mask and/or wafer are then positioned such that the signals generated from the alignment patterns indicate that the corresponding points on the mask and wafer are aligned.

Semiconductor wafer fracturing technique employing a pressure controlled roller

Abstract: A technique for fracturing a scribed wafer into its individual electronic circuit dice wherein a roller is passed over the wafer two times in paths that are 90* to one another, the force of the roll during the second pass being less than the force of the roll during the first pass over the wafer. A vacuum-driven apparatus is disclosed for moving a roller over a scribed wafer and maintaining an optimum force of the roll against the wafer in order to reduce the number of dice having chipped edges.

Method of making thermo-compression-bonded semiconductor device

Abstract: In making a semiconductor device comprising a die of silicon, germanium or gallium arsenide, the bonding of the die onto a metal header (i.e., holding member) is made firmly without insertion of a conventional thin gold film therebetween, by depositing gold onto the bonding face of a slice, which is to be cut into the die, in such a manner that at least the surface of the deposited layer is gold or an alloy of gold containing small amounts of an additive.

Connection means for semiconductor components and integrated circuits

Abstract: In a semiconductor wafer having an epitaxial layer on which circuit elements are formed, through-connections for said circuit elements to contacts formed on the opposite surface of the layer are provided by tapered high conductivity semiconductor regions insulated from the body by a thin layer of dielectric material and in contact with suitably doped portions of the epitaxial layer to provide insulation by means of reversely biased junctions.

Apparatus for producing ion-free insulating layers

Abstract: ION CONTAMINATION OF INSULATORS, SUCH AS THERMALLY GROWN SILICON DIOXIDE LAYERS ON SILICON WAFERS IS VIRTUALLY ELIMINATED, IF, AFTER OXIDE GROWTH, THE WAFERS ARE COOLED IN AN ION-FREE ZONE. A CYLINDRICAL, INNER, QUARTZ SLEEVE, PREFERABLY BAFFLED, IS INTERPOSED BETWEEN THE REACTION TUBE AND A WAFER CONTAINING BOAT WHILE A PURGING GAS SUCH AS ARGON, NITROGEN, HELIUM AND OTHER INERT GASES IS DIRECTED INTO THE SLEEVE OVER THE OXIDIZED WAFERS TO PREVENT CONTAMINATION OF THE WAFER BY IONS OUT-GASSING FROM THE WALLS OF THE REACTION TUBE DURING THE COOLING CYCLE. ALTERNATIVELY, THE PORTION OF THE TUBE DESIGNATED FOR WAFER COOLING IS CONTINUOUSLY BAKED BEFORE SAID DURING THE OXIDE GROWTH PROCESS AND COOLED SIMULTANEOUSLY WITH THE WAFERS THEREBY PREVENTING THE BUILDUP OF IONS ON THE WALLS IN THE WAFTER COOLING PORTION OF THE TUBE. ALTERNATIVELY, A QUARTZ SLEEVE IS INTERPOSED BETWEEN THE WAFER BOAT AND REACTION TUBE AND EXTENDS FROM THE HOT ZONE AND THROUGH THE PORTION OF THE TUBE DESIGNATED FOR WAFER COOLING. THE INNER SLEEVE IS REMOVED FOR WAFER COOLING.

Protective electrical feed through assemblies for enclosures for electrical devices

Abstract: A wafer of metallic oxide varistor material having a pair of opposed surfaces is provided with a plurality of apertures, each extending through the wafer from one opposed surface to the other opposed surface thereof. Each of the apertures are adapted to receive a respective conductive electrode of an electrical device and provide conductive contact between each of the electrodes and the wafer. The material has an alpha in excess of 10 when the current is of the current density range of 10 3 to 102 amperes per square centimeter. The proportions of the apertures of the wafer in contact with the electrodes are spaced to provide a current flow between a pair of electrodes which is low when normal operating voltages appear across the pair of electrodes and when voltages in excess of the normal voltage appear across the electrodes a rapidly decreasing impedance is presented by the wafer in accordance with the alpha of the material of the wafer thereby limiting the voltage across the electrodes.

Wafer transport system

Abstract: A transport system for semiconductor wafers and similar articles includes a transporter for the wafers, apparatus which introduces wafers to the transporter at one of its ends, a receiver for the wafers at the other end of the transporter, and apparatus for stacking two wafers during their passage along the transporter between the introducing apparatus and the receiver. The transporter is desirably an air slide, and a first wafer is stopped within the air slide by detaining pins that may be moved into the wafer path. A second wafer is then deflected by vertical air jets to lift it over the first wafer, where it is then stopped by the detaining pins and settles gently on top of the first wafer. If the air slide is bi-directional, the system may also include a wafer unstacker which receives the wafers from the receiver, then returns them to the introducing apparatus. This may be done with detaining pins of the same type used in the stacking apparatus and a Bernoulli pickup to restrain one of the wafers during unstacking. Such a system allows integrated circuit wafers to be stacked and unstacked without contacting a surface on each wafer in which the integrated circuits are being manufactured.

Electrochemically Thinned N/N+ Epitaxial Silicon—Method and Applications

Abstract: The method of thinning n/n+ epitaxial silicon wafers by selective anodic dissolution of the substrate in aqueous is described. Some of the properties of the system are discussed and applications are presented. It appears the technique is best suited for use where the material has not had extensive prior processing, especially n+ diffusions, and/or where the epitaxial layer is of high resistivity. The most promising areas of application appear to be: (a) fabrication of thin films for experimental purposes, (b) thinning of simple diode arrays, and (c) solid dielectric isolated IC fabrication. Considerable impediments to use of the process are the necessity of having epitaxial layers of unusual perfection and the fact that local anodic etching occurs at sites of high carrier generation.

Method for reducing crystallographic defects in semiconductor structures

Abstract: A method for fabricating semiconductor structures, wafer and devices with reduced thermally induced crystallographic defects comprising (a) supporting said wafers in close proximity to one another, (b) heating said wafers to an elevated temperature, (c) maintaining a uniform circumferential heat mass surrounding said wafers, (d) immediately withdrawing said material from the heating zone, and (e) symmetrically cooling said wafers.

Apparatus for polishing wafers

Abstract: An improved vacuum chuck for holding a thin fragile workpiece, such as a silicon wafer used as an electronic component, as the workpiece is being polished. The improved chuck has a removable and replaceable ring surrounding the workpiece to hold the workpiece in the event of an accidental loss of vacuum, and the chuck is grooved to distribute the differential pressure across the wafer over the entire wafer to avoid distortion due to localized pressure differences. The increased holding power of the chuck permits the use of higher downward pressures on the workpiece which speeds the polishing action both by increased abrasion and by increased chemical erosion which is accelerated by the higher heat of friction.

Method of making a semiconductor device

Abstract: PORTIONS OF A POLYCRYSTALLINE SILICON LAYER DISPOSED OF A SILICON DIOXIDE INSULATING LAYER ON A SEMICONDUCTOR WAFER ARE REMOVED AFTER DIFFUSING BORON INTO AND THROUGH THE REGIONS TO BE RETAINED. GOOD EDGE DEFINITION OF THE RETAINED SILICON AND IMPROVED YIELDS RESULTING FROM FEWER OXIDE PINHOLES ARE ACHIEVED.

Method and apparatus for positioning patterns of a photographic mask on the surface of a wafer on the basis of backside patterns of the wafer

Abstract: In the fabrication of a semiconductor device, an operation for positioning patterns of a photographic mask on the surface of a wafer with reference to metal-placed patterns on the underside of the wafer is remarkably improved by means of a microscopical method utilizing at least one pair of object lenses facing each other so that corresponding images of the basic patterns of the wafer and images of patterns of the photographic mask are taken separately, whereupon these images are then optically superimposed and observed. The metal-plated patterns are illuminated at an angle of incidence greater than zero in order to prevent reflective disturbance due to the support device for the wafer and the position of the photographic mask relative to the wafer is accurately adjusted while observing the abovementioned combined images.

Schottky contact devices and method of manufacture

Abstract: A method is described for making plural semiconductor devices containing a Schottky contact by providing on one side of a semiconductor wafer a metal layer to form the Schottky contact, and then subjecting the opposite side of the wafer to an etching treatment which attacks the semiconductor but not the Schottky metal until semiconductor portions are etched away leaving spaced semiconductor islands whose contact surface with the Schottky method is surrounded by free surface portions of the metal. Then the metal layer is severed along lines spaced from the islands to leave in the final device, an exposed metal surround to increase the breakdown voltage.

Laser scriber control system

Abstract: A laser scribe system is disclosed for aligning a wafer on which circuits are deposited, and for controlling the motion of a chuck, supporting the wafer, so that kerfs are cut in the wafer between all the circuits. The chuck is movable along X and Y axes in a XY plane by two indexable stepping motors, with a laser providing a beam in a direction perpendicular to the XY plane. The system is operable in an Align mode in which the chuck is movable back and forth in the X axis and the chuck is rotatable about an axis perpendicular to the XY plane until streets, representing wafer space between circuits, are aligned in the X axis. The system automatically sequences through several scribing phases during which the chuck is moved automatically in the X and Y axes at optimum speed to cut kerfs in all the streets of the wafer.

Method of dividing wafers

Abstract: A method of dividing silicon wafers includes the steps of marking a predetermined pattern on the wafer to be divided and applying a clear dielectric film over the marked surface thereof. The surface of the wafer is cut through the dielectric film along the pattern with the resulting debris being scattered over the protective film. The protective film along with the debris is then removed, for example, by washing in an appropriate solvent. The wafer is then broken along the cut surface for further processing.

Method for manufacturing a semiconductor integrated circuit isolated through dielectric material

Abstract: A METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT COMPRISES STEPS OF FORMING AN ENCLOSED GROOVE IN THE SURFCE OF A SEMICONDUCTOR WAFER, FORMING AN INNER DIELECTRIC LAYER ON THE SURFACE OF THE GROOVE, DEPOSITING AN EPITAXIAL LAYER ON SAID SURFACE OF THE WAFER AND THE SURFACE OF THE DIELECTRIC LAYER, FORMING AN OUTER DIELECTRIC LAYER ON THE EPITAXIAL LAYER, FORMING A SUPPORT SUBSTRATE ON THE OUTER DIELECTRIC LAYER, REMOVING THE WAFER IN A PREDETERMINED LEVEL TO FORM AN ISLAND REGION ENCLOSED BY THE OUTER DIELECTRIC LAYER AND FORMING A SEMICONDUTOR ELEMENT IN THE ISLAND REGION.

Vacuum holding apparatus

Abstract: Automatically operated vacuum chuck apparatus employs fluidic logic selectively to retain semiconductor wafers or parts of broken wafers during processing. The chuck has vacuum connectors communicating with ports in a retaining surface that holds the wafer or part of the wafer. Individual fluidic logic circuits are connected in parallel to respective ones of these connectors and ports and in common to vacuum and pressure supplies. On apparatus actuation, those ports covered by the wafer or part thereof are sensed and vacuum is applied only to these ports under the control of the individual fluidic logic circuits.

Alignment and bonding method for semiconductor components

Abstract: A method for bonding semiconductor structures of the type including semiconductor devices and bonding pads to lead structures. A semiconductor wafer containing a plurality of the lead structures is adhesively secured to a perforated die carrier with the wafer aligned so that a perforation underlies each semiconductor structure. The semiconductor wafer is then separated into individual semiconductor structures. An indexing mechanism positions the die carrier and hence the wafer so that one of the semiconductor structures is aligned with a bonding position. Another indexing mechanism positions a sheet of lead structures so that one of the lead structures is aligned with the bonding position. Due to orientation of the die carrier and the sheet of lead structures the bonding pads of the semiconductor structure in the bonding position are aligned with the spaced leads of the lead structure and the bonding position. A vacuum chuck travels up through the perforation in the die carrier and carries the semiconductor structure to the lead structure where it is bonded.

Photoresist keys and depth indicator

Abstract: A METHOD IS DISCLOSED FOR PROVIDING MEANS FOR ORIENTING AND POSITIONING A PHOTORESIST MASK ON A SEMICONDUCTOR WAFER AND FOR INDICATING THE DEPTH OF AN EPITAXIAL DEPOSIT. THIS MEANS COMPRISES FILLED HOLES CALLED KEYS WHICH ARE EASILY NOTED EVEN THOUGH THE SURFACE OF THE WAFER IS CAREFULLY POLISHED. SINCE THE DEPTH OF THE KEYS IS LESS BY A PREDETERMINED AMOUNT THAN THE DEPTH OF THE EPITAXIAL DEPOSIT, PRESENCE OF THE DEYS AFTER THE POLISHING STEP INDICATES THAT THE REMAINING DEPTH OF THE DEPOSIT IS GREAT ENOUGH TO MAKE APPLICATION OF OTHER PROCESS STEPS TO THE WAFER ADVISALBE AND THE KEYS THEMSELVES ARE USED FOR POSITIONING AND ORIENTING SUCH FIXTURES AS MASKING DEVICES ON THE SURFACE OF THE WAFER. D R A W I N G

Use of vapor deposition to form a hollow tubular body closed on one end

Abstract: BODY IS COVERED BY A WAFER FROM THE SAME SEMICONDUCTOR MATERIAL WHOSE SHAPE CORRESPONDS TO THE OPEN SIDE. THEREAFTER, THE SEMICONDUCTOR MATERIAL IS PRECIPITATED FROM THE GASEOUS COMPOUND UNTIL THE DESIRED LAYER THICKNESS AND A GAS-TIGHT CONNECTION IS OBTAINED BETWEEN THE LAYER AND THE COVERING SEMICONDUCTOR MATERIAL. THE SECOND METHOD PRECIPITATES A SEMICONDUCTOR LAYER AND THEREAFTER WELDS A COVER ON THE TUBE. DESCRIBED ARE TWO METHODS OF PRODUCING A HOLLOW BODY, COMPRISED OF SEMICONDUCTOR MATERIAL, ESPECIALLY SILICON, BY PRECIPITATION FROM A GASEOUS COMPOUND OF SAID SEMICONDUCTOR MATERIAL UPON THE SURFACE OF A HEATED CARRIER BODY, WHICH AFTER A SUFFICIENTLY THICK LAYER OF SEMICONDUCTOR MATERIAL HAS BEEN PRECIPITATED, IS REMOVED AGAIN WITHOUT DAMAGING SAID LAYER. ONE METHOD IS CHARACTERIZED BY USING A HOLLOW CARRIER BODY, OPEN AT LEAST AT TWO OPPOSITE SIDES. PRIOR TO THE PRECIPITATION OF THE SEMICONDUCTOR MATERIAL, ONE OF THE OPEN SIDES OF THE CARRIER

Method and apparatus for determining the thermal internal resistance in semiconductors of the same type

Abstract: For determining the internal thermal resistance of a semiconductor wafer, an arrangement is provided in which a metal member supports the bottom of the wafer and a thermosensor contacts the underside of the member and monitors heat transfer from the wafer to the support member which is a function of the internal thermal resistance of the semiconductor. A current pulse is fed to the semiconductor causing heat to generate therein. The detected time interval between cessation of the pulse and detection of maximum heat transfer to the thermosensor leads to determination of the internal thermal resistance.

Electromigration resistant metallization for integrated circuits, structure and process

Abstract: The exposed surfaces of metal leads formed on an integrated circuit wafer are anodized to reduce electromigration

Thin single crystal silicon on an insulating substrate and improved dielectric isolation processing method

Abstract: A METHOD IS DISCLOSED WHEREBY BY KINCORPORATING A P+ BORON LAYER OF 5X10**19 ATOMS PER CUBIC CENTIMETER OR GREATER ADDED DURING THE FABRICATION OF A WAFER ACTS AS AN ETCH STOP FOR A POTASSIUM HYDROXIDE ANISOPTROPIC ETCH SOLUTION (KOH). THEREBY THIN CONTROLLED LAYERS OF SINGLE CRYSTAL SILICON ON AN ISULATING SUBSTRATE CAN BE MADE. SIMILARLY USING THE SAME ETCH STOP DIELECTRICALLY ISOLATED ISLANDS OF SINGLE CRYSTAL SILICON MAY BE FORMED WITH IMPROVED YIELDS AND THICKNESS CONTROL.

Heat treating process for semiconductor fabrication

Abstract: A method and means for heat treating semiconductor material used in diffusion processes or in any semiconductor fabrication process, when the temperature of the semiconductor material exceeds its plastic temperature, for minimizing stresses caused by temperature gradients in the material whereby a number of harmful dislocations, which result in undesired electrical characteristics for the semiconductor circuits on the wafer are eliminated.

Method for fabricating semiconductor devices

Abstract: A plurality of individual semiconductor devices are simultaneously produced by thinning a doped semiconductor wafer to a desired uniform thickness, thermocompression bonding the thinned semiconductor wafer to a metal support plate, etching the wafer into many tiny discrete members, and punching out small individual sections of the support plate, each section forming a heat sink and having one of the bonded semiconductor members thereon Alternately, the semiconductor wafer may be thinned after the bonding step has been effected, although prior thinning is preferred