A
A. Shahani
Researcher at Stanford University
Publications - 11
Citations - 541
A. Shahani is an academic researcher from Stanford University. The author has contributed to research in topics: CMOS & Noise figure. The author has an hindex of 8, co-authored 11 publications receiving 531 citations.
Papers
More filters
Journal ArticleDOI
A 12 mW wide dynamic range CMOS front end for a portable GPS receiver
TL;DR: In this paper, a CMOS low-noise amplifier (LNA) and mixer intended for use in the front-end of a global positioning system (GPS) receiver were implemented in a standard 0.35/spl mu/m (drawn) CMOS process.
Journal ArticleDOI
A 115-mW, 0.5-/spl mu/m CMOS GPS receiver with wide dynamic-range active filters
D.K. Shaeffer,A. Shahani,S.S. Mohan,H. Samavati,H.R. Rategh,M. del Mar Hershenson,Min Xu,Chik Patrick Yue,D.J. Eddleman,Thomas H. Lee +9 more
TL;DR: In this paper, the authors present a 115mW Global Positioning System radio receiver that is implemented in a 0.5/spl mu/m CMOS technology, which includes the complete analog signal path, comprising a low-noise amplifier, I-Q mixers, on-chip active filters, and 1-bit analog-digital converters.
Journal ArticleDOI
A 40-43-Gb/s clock and data recovery IC with integrated SFI-5 1:16 demultiplexer in SiGe technology
A. Ong,S. Benyamin,J. Cancio,V. Condito,T. Labrie,Qinghung Lee,J.P. Mattia,D.K. Shaeffer,A. Shahani,Xiaomin Si,Hai Tao,M. Tarsia,W. Wong,Min Xu +13 more
TL;DR: A fully integrated OC-768 clock and data recovery IC with SFI-5 1:16 demultiplexer is designed in a 120 GHz/100 GHz (f/sub T//f/ sub max/) SiGe technology.
Patent
Method and apparatus for a lateral flux capacitor
TL;DR: Fractal shapes can be used to maximize the length of the perimeter of adjacent capacitor conductive components in a single metal layer as mentioned in this paper, where the Koch Islands and Minkowski Sausage families of fractals are particularly well suited for generating capacitor-conductive component perimeter shapes.
Journal ArticleDOI
40-43-Gb/s OC-768 16:1 MUX/CMU chipset with SFI-5 compliance
Hai Tao,D.K. Shaeffer,Min Xu,S. Benyamin,V. Condito,S. Kudszus,Qinghung Lee,A. Ong,A. Shahani,Xiaomin Si,W. Wong,M. Tarsia +11 more
TL;DR: This chipset accommodates 11 bits of static skew and 21 bits of dynamic wander at the SFI-5 interface, while generating 125 fs rms of random jitter and 3.1 ps peak-to-peak of deterministic jitter at its 40-43-Gb/s outputs.