Injection locking characteristics of oscillators are derived and a graphical analysis is presented that describes injection pulling in time and frequency domains. An identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction. The behavior of phase-locked oscillators under injection pulling is also formulated.

/pdf/a-study-of-injection-locking-and-pulling-in-oscillators-43lsvme4nh.pdf

A study of injection locking and pulling in oscillators

This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques. Based on the noise parameter equations, this paper provides clear understanding of the design principles, fundamental limitations, and advantages of the four reported LNA design techniques so that the designers can get the overall LNA design perspective. As a demonstration for the proposed design principle of the PCSNIM technique, a very low-power folded-cascode LNA is implemented based on 0.25-/spl mu/m CMOS technology for 900-MHz Zigbee applications. Measurement results show the noise figure of 1.35 dB, power gain of 12 dB, and input third-order intermodulation product of -4dBm while dissipating 1.6 mA from a 1.25-V supply (0.7 mA for the input NMOS transistor only). The overall behavior of the implemented LNA shows good agreement with theoretical predictions.

/pdf/cmos-low-noise-amplifier-design-optimization-techniques-42bhmxri1r.pdf

CMOS low-noise amplifier design optimization techniques

The concept of concurrent multiband low-noise-amplifiers (LNAs) is introduced. A systematic way to design concurrent multiband integrated LNAs in general is developed. Applications of concurrent multiband LNAs in concurrent multiband receivers together with receiver architecture are discussed. Experimental results of a dual-band LNA implemented in a 0.35-/spl mu/m CMOS technology as a demonstration of the concept and theory is presented.

/pdf/concurrent-multiband-low-noise-amplifiers-theory-design-and-1iy48rdapl.pdf

Concurrent multiband low-noise amplifiers-theory, design, and applications

A highly integrated 175-GHz 035-/spl mu/m CMOS transmitter is described The I/Q modulator-based transmitter facilitates integration through the use of a unique mixer, termed a harmonic-rejection mixer, and a wide loop bandwidth phase-locked loop (PLL) for the RF synthesizer The harmonic-rejection mixers are used to eliminate the need for a discrete IF filter and the use of a wide loop bandwidth PLL allowed for the complete integration of the synthesizers using low-Q components while achieving low phase noise The entire transmit signal path from the digital-to-analog converters to the power amplifier, including two fully integrated frequency synthesizers, is integrated into a single-chip solution The transmitter was tested with a testing buffer before the power amplifier (PA) and achieved less than 13/spl deg/ rms phase error when modulating a DCS-1800 GMSK signal The prototype consumed 151 mA from a 3-V supply A class-C PA, capable of driving 25 dBm off-chip, was included and the output was compared to the testing buffer with little change in the transmitter performance

A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers

Injection-locked oscillators (ILOs) are investigated in a new theoretical approach. A first-order differential equation is derived for the noise dynamics of ILOs. A single-ended injection-locked frequency divider (SILFD) is designed in a 0.5-/spl mu/m CMOS technology operating at 1.8 GHz with more than 190 MHz locking range while consuming 3 mW of power. A differential injection-locked frequency divider (DILFD) is designed in a 0.5-/spl mu/m CMOS technology operating at 3 GHz and consuming 0.45 mW, with a 190 MHz locking range. A locking range of 370 MHz is achieved for the DILFD when the power consumption is increased to 1.2 mW.

/pdf/superharmonic-injection-locked-frequency-dividers-jgrgw5ct77.pdf

Superharmonic injection-locked frequency dividers

This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-/spl mu/m CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm.

/pdf/a-5-ghz-cmos-wireless-lan-receiver-front-end-x13hqw0dbw.pdf

A 5-GHz CMOS wireless LAN receiver front end

Injection-locked frequency dividers (ILFDs) are versatile analog circuit blocks used, for example, within phase-locked loops (PLLs). An important attribute is substantially lower power consumption relative to their digital counterparts. The model described in this paper unifies the treatment of injection-locked and regenerative systems. It also provides useful design insights by clarifying the nature and role of the nonlinearity present in many mixer-based frequency conversion circuits. The utility of the model is demonstrated in the calculation of both the steady-state and dynamic properties of ILFD systems, and the subsequent computation of the corresponding phase noise spectrum. Illustrative circuit examples show close correspondence between theory and simulation. Finally, measurement results from a 5.4-GHz divide-by-2 ILFD fabricated in 0.24-/spl mu/m CMOS show close correspondence between experiment and theory.

/pdf/a-unified-model-for-injection-locked-frequency-dividers-2tfg3tq9b4.pdf

A unified model for injection-locked frequency dividers

A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24 /spl mu/m CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. On-chip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of -101 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than -54 dBc.

/pdf/a-cmos-frequency-synthesizer-with-an-injection-locked-2877a28dh5.pdf

A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver

This paper first provides an overview of some recently ratified wireless local-area network (WLAN) standards before describing an illustrative 5-GHz WLAN receiver implementation. The receiver, built in a standard 0.25-/spl mu/m CMOS logic technology, exploits several recent developments, including lateral-flux capacitors, accumulation-mode varactors, injection-locked frequency dividers, and an image-reject low-noise amplifier. The receiver readily complies with the performance requirements of both IEEE 802.11a and ETSI HiperLAN. It exhibits a 7.2-dB noise figure, as well as an input-referred third-order intercept and 1-dB compression point of -7 and -18 dBm, respectively. Image rejection for this double conversion receiver exceeds 50 dB throughout the frequency band without using external filters. Leakage out of the RF port from the local oscillators is under -87 dBm, and all synthesizer spurs are below the -70-dBm noise floor of the instrumentation used to measure them. The receiver consumes 59 mW from a 1.8-V supply and occupies only 4 mm/sup 2/ of die area, in no small measure due to the use of fractal capacitors for ac coupling.

H.R. Rategh

Papers

Superharmonic injection-locked frequency dividers

A 5-GHz CMOS wireless LAN receiver front end

A unified model for injection-locked frequency dividers

A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver

5-GHz CMOS wireless LANs