A
Ahmed Elkholy
Researcher at University of Illinois at Urbana–Champaign
Publications - 49
Citations - 873
Ahmed Elkholy is an academic researcher from University of Illinois at Urbana–Champaign. The author has contributed to research in topics: Jitter & Phase-locked loop. The author has an hindex of 15, co-authored 48 publications receiving 641 citations. Previous affiliations of Ahmed Elkholy include Broadcom & Xilinx.
Papers
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A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
TL;DR: The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution and is less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL.
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A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition
Guanghua Shu,Woo-Seok Choi,Saurabh Saxena,Mrunmay Talegaonkar,Tejasvi Anand,Ahmed Elkholy,Amr Elshazly,Pavan Kumar Hanumolu +7 more
TL;DR: A ring-oscillator-based two-stage fractional-N phase-locked loop (PLL) is used as a digitally controlled oscillator (DCO) to achieve wide frequency range, low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring oscillator noise suppression in conventional CDRs.
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A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider
TL;DR: This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization Noise.
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Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers
TL;DR: This paper introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection-locked oscillators (ILOs) and captures the asymmetric nature of ILO's lock-in range, and the impact of frequency error on injection strength and phase noise performance.
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A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method
Romesh Kumar Nandwana,Tejasvi Anand,Saurabh Saxena,Seong Joong Kim,Mrunmay Talegaonkar,Ahmed Elkholy,Woo-Seok Choi,Amr Elshazly,Pavan Kumar Hanumolu +8 more
TL;DR: A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs and alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression.