A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider
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TLDR
This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization Noise.Abstract:
Phase noise performance of ring oscillator based digital fractional-N phase-locked loops (FNPLLs) is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the time-to-digital converter (TDC), $\Delta \Sigma $ fractional divider, and digital-to-analog converter (DAC). As a consequence, their figure-of-merit (FoMJ) that quantifies the power–jitter tradeoff is at least 25 dB worse than their LC-oscillator-based FNPLL counterparts. This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. Fabricated in 65 nm CMOS process, the proposed FNPLL operates over a wide frequency range of 2.0–5.5 GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9 psrms integrated jitter while consuming only 4 mW at 5 GHz output. The measured in-band phase noise is better than −96 dBc/Hz at 1 MHz offset. The proposed FNPLL achieves wide BW up to 6 MHz using a 50 MHz reference and its FoMJ is −228.5 dB, which is the best among all reported ring-based FNPLLs.read more
Citations
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TL;DR: A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is presented that employs a background-calibrated reference frequency doubler to increase the RO noise suppression bandwidth, a digital delay-locked loop to achieve second-order suppression of RO noise, and a digital frequency-tracking loop to continuously tune the oscillator’s free-running frequency.
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A 50–66-GHz Phase-Domain Digital Frequency Synthesizer With Low Phase Noise and Low Fractional Spurs
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A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order $\Delta \Sigma$ Linearization
TL;DR: An 8-bit 1.25-ps resolution reconfigurable Vernier time-to-digital converter (TDC) with a 2-D spiral comparator array and $\Delta \Sigma $ modulators for linearization is presented.
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A Fractional- $N$ PLL With Space–Time Averaging for Quantization Noise Reduction
Yanlong Zhang,Arindam Sanyal,Xueyi Yu,Xing Quan,Kailin Wen,Xiyuan Tang,Gang Jin,Li Geng,Nan Sun +8 more
TL;DR: A space–time averaging technique that can realize instantaneous fractional frequency division, and thus, can significantly reduce the quantization error in a fractional- $N$ phase-locked loop (PLL).
References
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TL;DR: In this article, a delay-locked loop (DLL) and phase-locked loops (PLL) designs based upon self-biased techniques are presented, which achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and low input tracking jitter.
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A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology
TL;DR: In this article, a modular and power-scalable architecture for low-power programmable frequency dividers is presented, which consists of a 17-bit UHF divider, an 18-bit L-band divider and a 12-bit reference divider.
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A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation
TL;DR: A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz bandwidth is presented, which uses a gated-ring-oscillator time-to-digital converter to achieve integrated phase noise of less than 300 fs.