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Woo-Seok Choi
Researcher at University of Illinois at Urbana–Champaign
Publications - 30
Citations - 679
Woo-Seok Choi is an academic researcher from University of Illinois at Urbana–Champaign. The author has contributed to research in topics: Phase-locked loop & Jitter. The author has an hindex of 10, co-authored 30 publications receiving 429 citations. Previous affiliations of Woo-Seok Choi include Harvard University & Seoul National University.
Papers
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Journal ArticleDOI
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
TL;DR: The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution and is less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL.
Journal ArticleDOI
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition
Guanghua Shu,Woo-Seok Choi,Saurabh Saxena,Mrunmay Talegaonkar,Tejasvi Anand,Ahmed Elkholy,Amr Elshazly,Pavan Kumar Hanumolu +7 more
TL;DR: A ring-oscillator-based two-stage fractional-N phase-locked loop (PLL) is used as a digitally controlled oscillator (DCO) to achieve wide frequency range, low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring oscillator noise suppression in conventional CDRs.
Posted Content
Cheetah: Optimizing and Accelerating Homomorphic Encryption for Private Inference
Brandon Reagen,Woo-Seok Choi,Yeongil Ko,Vincent T. Lee,Gu-Yeon Wei,Hsien-Hsin S. Lee,David Brooks +6 more
TL;DR: This paper introduces Cheetah, a set of algorithmic and hardware optimizations for server-side HE DNN inference, and finds that privacy-preserving HE inference for ResNet50 can approach real-time speeds with a 587mm2 accelerator dissipating 30W in 5nm.
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A 10-MHz 2–800-mA 0.5–1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes
TL;DR: This work explores pulse frequency modulation (PFM) that is commonly used to improve light load efficiency in voltage-mode controllers and extends its operation to time-based controllers to maintain high efficiency even in the presence of dynamic load variations.
Journal ArticleDOI
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method
Romesh Kumar Nandwana,Tejasvi Anand,Saurabh Saxena,Seong Joong Kim,Mrunmay Talegaonkar,Ahmed Elkholy,Woo-Seok Choi,Amr Elshazly,Pavan Kumar Hanumolu +8 more
TL;DR: A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs and alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression.