M
Mrunmay Talegaonkar
Researcher at University of Illinois at Urbana–Champaign
Publications - 32
Citations - 838
Mrunmay Talegaonkar is an academic researcher from University of Illinois at Urbana–Champaign. The author has contributed to research in topics: Phase-locked loop & Jitter. The author has an hindex of 15, co-authored 32 publications receiving 699 citations. Previous affiliations of Mrunmay Talegaonkar include Oregon State University.
Papers
More filters
Journal ArticleDOI
A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer
Karthikeyan Reddy,Sachin Rao,Rajesh Inti,Brian Young,Amr Elshazly,Mrunmay Talegaonkar,Pavan Kumar Hanumolu +6 more
TL;DR: A continuous-time (CT) ΔΣ modulator using a VCO-based internal quantizer that incorporates a nonlinear VCO as the second stage in a two-stage residue canceling quantizer (RCQ) and mitigates the impact of its nonlinearity by spanning only a small region of the VCO's V-to-F nonlinear tuning curve.
Journal ArticleDOI
Analog Filter Design Using Ring Oscillator Integrators
TL;DR: This work proposes applying ring oscillator integrators (ROIs) in the design of high order analog filters to achieve infinite DC gain at low supply voltages independent of transistor non-idealities and imperfections such as finite output impedance.
Journal ArticleDOI
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition
Guanghua Shu,Woo-Seok Choi,Saurabh Saxena,Mrunmay Talegaonkar,Tejasvi Anand,Ahmed Elkholy,Amr Elshazly,Pavan Kumar Hanumolu +7 more
TL;DR: A ring-oscillator-based two-stage fractional-N phase-locked loop (PLL) is used as a digitally controlled oscillator (DCO) to achieve wide frequency range, low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring oscillator noise suppression in conventional CDRs.
Proceedings ArticleDOI
A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer
Karthikeyan Reddy,Sachin Rao,Rajesh Inti,Brian Young,Amr Elshazly,Mrunmay Talegaonkar,Pavan Kumar Hanumolu +6 more
TL;DR: This ADC overcomes the impact of VCO non-linearity by minimizing the input signal processed by the VCO, which achieves 78.3dB SNDR in a 10MHz signal bandwidth at 600MHz sampling rate, while consuming 16mW power.
Journal ArticleDOI
High Frequency Buck Converter Design Using Time-Based Control Techniques
Seong Joong Kim,Qadeer A. Khan,Mrunmay Talegaonkar,Amr Elshazly,Arun Rao,Nathanael Griesert,Greg Winter,William J. McIntyre,Pavan Kumar Hanumolu +8 more
TL;DR: Time-based control techniques for the design of high switching frequency buck converters are presented and eliminates the need for wide bandwidth error amplifier, pulse-width modulator (PWM) in analog controllers or high resolution analog-to-digital converter (ADC) and digital PWM in digital controllers.